Various computational approaches from rule-based to model-based methods exist to place Sub-Resolution Assist Features (SRAF) in order to increase process window for lithography. Each method has its advantages and drawbacks, and typically requires the user to make a trade-off between time of development, accuracy, consistency and cycle time.
Rule-based methods, used since the 90 nm node, require long development time and struggle to achieve good process window performance for complex patterns. Heuristically driven, their development is often iterative and involves significant engineering time from multiple disciplines (Litho, OPC and DTCO).
Model-based approaches have been widely adopted since the 20 nm node. While the development of model-driven placement methods is relatively straightforward, they often become computationally expensive when high accuracy is required. Furthermore these methods tend to yield less consistent SRAFs due to the nature of the approach: they rely on a model which is sensitive to the pattern placement on the native simulation grid, and can be impacted by such related grid dependency effects. Those undesirable effects tend to become stronger when more iterations or complexity are needed in the algorithm to achieve required accuracy.
ASML Brion has developed a new SRAF placement technique on the Tachyon platform that is assisted by machine learning and significantly improves the accuracy of full chip SRAF placement while keeping consistency and runtime under control. A Deep Convolutional Neural Network (DCNN) is trained using the target wafer layout and corresponding Continuous Transmission Mask (CTM) images. These CTM images have been fully optimized using the Tachyon inverse mask optimization engine. The neural network generated SRAF guidance map is then used to place SRAF on full-chip. This is different from our existing full-chip MB-SRAF approach which utilizes a SRAF guidance map (SGM) of mask sensitivity to improve the contrast of optical image at the target pattern edges.
In this paper, we demonstrate that machine learning assisted SRAF placement can achieve a superior process window compared to the SGM model-based SRAF method, while keeping the full-chip runtime affordable, and maintain consistency of SRAF placement . We describe the current status of this machine learning assisted SRAF technique and demonstrate its application to full chip mask synthesis and discuss how it can extend the computational lithography roadmap.
Sub-Resolution Assist Features (SRAF) are widely used for Process Window (PW) enhancement in computational
lithography. Rule-Based SRAF (RB-SRAF) methods work well with simple designs and regular repeated patterns, but
require a long development cycle involving Litho, OPC, and design-technology co-optimization (DTCO) engineers.
Furthermore, RB-SRAF is heuristics-based and there is no guarantee that SRAF placement is optimal for complex
patterns. In contrast, the Model-Based SRAF (MB-SRAF) technique to construct SRAFs using the guidance map is
sufficient to provide the required process window for the 32nm node and below. It provides an improved lithography
margin for full chip and removes the challenge of developing manually complex rules to assist 2D structures. The
machine learning assisted SRAF placement technique developed on the ASML Brion Tachyon platform allows us to
push the limits of MB-SRAF even further. A Deep Convolutional Neural Network (DCNN) is trained using a
Continuous Transmission Mask (CTM) that is fully optimized by the Tachyon inverse lithography engine. The neural
network generated SRAF guidance map is then used to assist full-chip SRAF placement. This is different from the
current full-chip MB-SRAF approach which utilizes a guidance map of mask sensitivity to improve the contrast of
optical image at the edge of lithography target patterns. We expect that machine learning assisted SRAF placement can
achieve a superior process window compared to the MB-SRAF method, with a full-chip affordable runtime significantly
faster than inverse lithography. We will describe the current status of machine learning assisted SRAF technique and
demonstrate its application on the full chip mask synthesis and how it can extend the computational lithography
To achieve the ultimate resolution and process control from an optical (193i 1.35NA) scanner system, it is desirable to be able to exploit both source and mask degrees of freedom to create the imaging conditions for any given set of patterns that comprise a photomask. For the source it has been possible to create an illumination system that allows for almost no restrictions in the location and intensity of source points in the illumination plane . For the mask, it has been harder to approach the ideal continuous phase and transmission mask that theoretically would have the best imaging performance. Mask blanks and processing requirements have limited us to binary (1 and 0 amplitude, or 1 and -0.25 amplitude (6% attenuated PSM)) or Alternating PSM (1, 0 and -1 amplitude) solutions. Furthermore, mask writing (and OPC algorithms) have limited us to Manhattan layouts for full chip logic solutions. Recent developments in the areas of mask design and newly developed Multi-Beam Mask Writers (MBMW) have removed the mask limitation to Manhattan geometries . In this paper we consider some of the manufacturing challenges for these curvilinear masks.