A pair of radiation hardened high-voltage mixed signal Application Specific Integrated Circuits (ASICs) are described that provide the biasing and clocking functions required to drive large format CCDs used for space-borne cameras and focal planes. The use of these ASICs allows the CCD drive electronics to be realised in a compact and energy efficient manner saving volume, mass, and power when compared with traditional space-qualified discrete implementations. The STAR ASIC provides 24 independent voltage outputs with a 32.736V range at 10 bit resolution and with <100μV noise. Each voltage output provides a drive current of up to +/-20mA and is stable for capacitive loads of up to 10μF. An on-board telemetry system featuring a 12-bit ADC and programmable gain buffer allows internal monitoring of the output voltages plus up to 32 single ended and 4 differential external voltages, such as from PRT bridge circuits for temperature monitoring. A simple SPI serial interface provides control and telemetry read back, while all required voltages and currents are generated from internal bandgap circuits. The COMET ASIC provides 6 fully independent clock buffering channels each with individually programmable rising/falling current drive and high/low voltage levels. Output voltage levels are controlled with integrated fast response regulators that operate over a 16.368V range without the need for external decoupling capacitors. Clock drive currents can be adjusted for the load capacitance and output slew rate required over a 409.6mA range, with edge speeds <15ns achievable for small loads. Setup and control of the ASIC is also via an SPI interface with integrated safety features to ensure correct sequencing of channel operation and to prevent reverse biasing of the driver programmable voltage supplies. The COMET ASIC also features an under-voltage lock out circuit to safeguard the chip in the event of unexpected power loss. All necessary biases are generated internally and only supply decoupling, a single filtering capacitor, and a resistive divider are required to operate the device. Both devices have been designed in a commercial 0.35μm 50V tolerant HV CMOS technology using Triple Module Redundancy (TMR) and established layout techniques to harden against Total Ionising Dose (TID), Single Event Upset (SEU), and Single Event Latch-up (SEL) radiation effects. The latch-up detection circuits often needed for space electronics are therefore not required for either ASIC. Details of the architectures and circuit implementations of both ASICs will be presented. Test results from manufactured devices will be shown under representative load conditions.
The CCD remains the preeminent visible and ultra-violet wavelength image sensor in space-science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and sufficient tolerance to the effects of space radiation.
We describe our programme to develop science-grade CMOS active pixel sensors for future space science missions, and in particular an extreme ultra-violet spectrograph for solar physics studies on the ESA Solar Orbiter. Our goal is the development of a large format 4k x 4k pixel CMOS sensor with useful sensitivity in the extreme ultra-violet (EUV) for solar physics spectroscopy and imaging. Our route to EUV sensitivity relies primarily in adapting the back-thinning and rear-illumination techniques first developed for CCD sensors; however we are also exploring the alternative approach of using a front-etch to expose the CMOS photodiodes. We have successfully back-thinned several 525 x 525 prototype CMOS sensors and proved that the devices survived the process both structurally and functionally. We have also been successful in removing the oxide from the front side of a small array of pixels, using focused ion beam etching. Preliminary results from these pixels show they are sensitive in the Ultra Violet. We have also designed a working large format 4k x 3k prototype on a 0.25 micron CMOS imager process.