Mr. Rachit Gupta Profile

Rachit Gupta

Product Manager at ASML

SPIE Involvement:

Author

Publications (13)

SPIE Journal Paper | 30 January 2024

Curvilinear data representation and its impact on file size and lithographic performance

Jiuning Hu, Adam Lyons, Chris Spence, Kurt Wampler, Mahmoud Mohsen, Yen-Wen Lu, Rachit Gupta, Youping Zhang, Rafael Howell, Jiyoon Chang, James Moon, Jun Ye

JM3, Vol. 23, Issue 01, 011204, (January 2024) https://doi.org/10.1117/12.10.1117/1.JMM.23.1.011204

KEYWORDS: Microchannel plates, Optical proximity correction, Lithography, Extreme ultraviolet, Deep ultraviolet, Solids, SRAF, Metals, Photovoltaics, Data storage

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Proceedings Article | 28 April 2023 Paper

Computational lithography solutions to support EUV high-NA patterning

Rongkuo Zhao, Fan Zhou, Jialei Tang, Jeff Lu, Yunbo Liu, Dezheng Sun, Ming-Chun Tien, Stephen Hsu, Rachit Gupta, Youping Zhang, Joerg Zimmermann

Proceedings Volume 12495, 124950R (2023) https://doi.org/10.1117/12.2660858

KEYWORDS: Source mask optimization, SRAF, Light sources and illumination, Extreme ultraviolet, 3D mask effects, Image quality, Computational lithography

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Proceedings Article | 28 April 2023 Presentation + Paper

Curvilinear data representation and its impact on file size and lithographic performance

Jiuning Hu, Adam Lyons, Chris Spence, Kurt Wampler, Mahmoud Mohsen, Yen-Wen Lu, Rachit Gupta, Youping Zhang, Rafael Howell, Jun Ye

Proceedings Volume 12495, 1249506 (2023) https://doi.org/10.1117/12.2658649

KEYWORDS: Optical proximity correction, Lithography, Extreme ultraviolet, Deep ultraviolet, Data storage

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Proceedings Article | 23 March 2020 Presentation + Paper

Machine learning techniques for OPC improvement at the sub-5 nm node

Changsoo Kim, Seungjong Lee, Sangwoo Park, No-Young Chung, Jungmin Kim, Narae Bang, Sanghwa Lee, SooRyong Lee, Robert Boone, Pengcheng Li, Jiyoon Chang, Xinxin Zhou, YoungMi Kim, MinSu Oh, Minsung Kim, Rachit Gupta, Jun Ye, Stanislas Baron

Proceedings Volume 11323, 1132317 (2020) https://doi.org/10.1117/12.2551841

KEYWORDS: Data modeling, Optical proximity correction, Performance modeling, Neural networks, Image processing, Machine learning, Lithography, Extreme ultraviolet, Photoresist processing, Statistical modeling

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Proceedings Article | 10 October 2019 Paper

Full-chip application of machine learning SRAFs on DRAM case using auto pattern selection

Kun-yuan Chen, Andy Lan, Richer Yang, Vincent Chen, Shulu Wang, Stella Zhang, Xiangru Xu, Andy Yang, Sam Liu, Xiaolong Shi, Angmar Li, Stephen Hsu, Stanislas Baron, Gary Zhang, Rachit Gupta

Proceedings Volume 10961, 1096108 (2019) https://doi.org/10.1117/12.2524051

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As technology continues to scale aggressively, Sub-Resolution Assist Features (SRAF) are becoming an increasingly key resolution enhancement technique (RET) to maximize the process window enhancement. For the past few technology generations, lithographers have chosen to use a rules-based (RB-SRAF) or a model-based (MB-SRAF) approach to place assist features on the design. The inverse lithography solution, which provides the maximum process window entitlement, has always been out of reach for full-chip applications due to its very high computational cost. ASML has developed and demonstrated a deep learning SRAF placement methodology, Newron™ SRAF, which can provide the performance benefit of an inverse lithography solution while meeting the cycle time requirements for full-chip applications [1]. One of the biggest challenges for a deep learning approach is pattern selection for neural network training. To ensure pattern coverage for maximum accuracy while maintaining turn-around time (TAT,) a deep-learning-based Auto Pattern Selection (APS) tool is evaluated. APS works in conjunction with Newron SRAF to provide the optimal lithography solution. In this paper, Newron SRAF is used on a DRAM layer. A Deep Convolutional Neural Network (DCNN) is trained using the target images and Continuous Transmission Mask (CTM) images. CTM images are gray tone images that are fully optimized by the Tachyon inverse mask optimization engine. Representative patterns selected by APS are used to train the neural network. The trained neural network generates SRAFs on the full-chip and then Tachyon OPC+ is performed to correct main and SRAF simultaneously. The neural network trained by APS patterns is compared with those trained by patterns from manual selection and multiple random selections to demonstrate its robustness on pattern coverage. Tachyon Hierarchical OPC+ (HScan+) is used to apply Newron SRAF at full-chip level in order to keep consistency and increase speed. Full-chip simulation results from Newron SRAF are compared with the baseline OPC flow using RBSRAF and MB-SRAF. The Newron SRAF flow shows significant improvements in NILS and PV band over the baseline flows. This whole flow including APS, Newron SRAF and full-chip HScan+ OPC enables the inverse mask optimization on full-chip level to achieve superior mask performance with production-affordable TAT.

Proceedings Article | 20 March 2018 Presentation + Paper

Freeform mask optimization using advanced image based M3D inverse lithography and 3D-NAND full chip OPC application

Yaobin Feng, Zhiyang Song, Moran Guo, Jun He, Longxia Guo, Gang Xu, Sam Liu, Jingjing Liu, Stephen Hsu, Austin Peng, Andy Yang, Rachit Gupta , Junwei Lu, Victor Peng, Jun Wang, Xiaolong Shi, Leon Liu, Rafael Howell, Cuiping Zhang , Zero Li, Ning-ning Jia

Proceedings Volume 10587, 105870G (2018) https://doi.org/10.1117/12.2297397

KEYWORDS: Photomasks, Source mask optimization, Optical proximity correction, Lithography, SRAF, Semiconducting wafers, Printing, Electroluminescence, Scanning electron microscopy, Pattern recognition

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Inverse lithography is increasingly being used as a viable OPC solution to maximize process window (PW), improve CD uniformity (CDU) and minimize the mask error factor (MEF), especially for memory devices. The device yield is typically limited by the process window of a few critical layers, and the Via layer is identified as one of the process window limiters for advanced 3D-NAND devices. To maximize the on-chip yield, ASML has developed advanced image based Mask-3D (M3D) inverse technology that can optimize freeform mask shapes and enhance design printability throughout the mask optimization flow. Mask rule checks (MRC) and side-lobe printing are optimized simultaneously to deliver the maximum process window.

The advanced image based M3D inverse lithography technology (ILT) is used to perform full chip mask correction on the Via layer of a 3D-NAND device. 3D NAND devices contain highly repetitive cell and page buffer patterns. To ensure the full chip device performance, the consistency of the mask correction is important. Our strategy is to use the computationally intensive mask optimization solution from the new advanced image based M3D inverse technology to generate a freeform mask which gives the best lithography performance. We then use Tachyon’s Pattern Recognition and Optimization (PRO) engine to propagate the freeform mask solution of the repetitive patterns to the full chip. The periphery of the chip is optimized using conventional OPC methods. The simulation results from the advanced image based M3D inverse technology are compared against the baseline flow, which uses a standard inverse solution. The simulation results from both the flows are further validated on wafer. Significant improvement in overlapping process window (OPW) and CD uniformity is observed using the new advanced inverse technology. The simulation data shows a 32% improvement in depth of focus (DOF), a 5% improvement in the image log slope (ILS) and a 25% reduction in best focus shift (BFS) range. The improvement has also been verified at the wafer-level.

SPIE Journal Paper | 27 April 2016

Two-layer critical dimensions and overlay process window characterization and improvement in full-chip computational lithography

John Sturtevant, Vlad Liubich, Rachit Gupta

JM3, Vol. 15, Issue 02, 021405, (April 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.2.021405

KEYWORDS: Metals, Critical dimension metrology, Overlay metrology, Optical lithography, Monochromatic aberrations, Optical proximity correction, Double patterning technology, Error analysis, Photomasks, Computational lithography

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Proceedings Article | 23 October 2015 Paper

Characterization and mitigation of relative edge placement errors (rEPE) in full-chip computational lithography

John Sturtevant, Rachit Gupta, Shumay Shang, Vlad Liubich, James Word

Proceedings Volume 9635, 963505 (2015) https://doi.org/10.1117/12.2196634

KEYWORDS: Metals, Optical lithography, Overlay metrology, Critical dimension metrology, Manufacturing, Monochromatic aberrations, Photomasks, Double patterning technology, Optical proximity correction, Computational lithography

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Edge placement error (EPE) was a term initially introduced to describe the difference between predicted pattern contour edge and the design target. Strictly speaking this quantity is not directly measurable in the fab, and furthermore it is not ultimately the most important metric for chip yield. What is of vital importance is the relative EPE (rEPE) between different design layers, and in the era of multi-patterning, the different constituent mask sublayers for a single design layer. There has always been a strong emphasis on measurement and control of misalignment between design layers, and the progress in this realm has been remarkable, spurned in part at least by the proliferation of multi-patterning which reduces the available overlay budget by introducing a coupling of alignment and CD errors for the target layer.

In-line CD and overlay metrology specifications are typically established by starting with design rules and making certain assumptions about error distributions which might be encountered in manufacturing. Lot disposition criteria in photo metrology (rework or pass to etch) are set assuming worst case assumptions for CD and overlay respectively. For example poly to active overlay specs start with poly endcap design rules and make assumptions about active and poly lot average and across lot CDs, and incorporate general knowledge about poly line end rounding to ensure that leakage current is maintained within specification. This worst case guard banding does not consider specific chip designs, however and as we have previously shown full-chip simulation can elucidate the most critical "hot spots" for interlayer process variability comprehending the two-layer CD and misalignment process window. It was shown that there can be differences in X versus Y misalignment process windows as well as positive versus negative directional misalignment process windows and that such design specific information might be leveraged for manufacturing disposition and control schemes.

This paper will further investigate examples of via-metal model-based analysis of CD and overlay errors. We will investigate both single patterning and double patterning. For single patterning, we show the advantage of contour to contour simulation over contour to target simulation, and how the addition of aberrations in the optical models can provide a more realistic PW window for edge placement errors. For double patterning, the interaction of 4 layer CD and misalignment errors is very complex, but we illustrate that not only can full-chip verification identify potential rEPE hotspots, the OPC engine can act to mitigate such hotspots and enlarge the overall combined CD-overlay rEPE process window.

SPIE Journal Paper | 11 September 2015

Directed self-assembly graphoepitaxy template generation with immersion lithography

Yuansheng Ma, Junjiang Lei, J. Andres-Torres, Le Hong, James Word, Germain Fenger, Alexander Tritchkov, George Lippincott, Rachit Gupta, Neal Lafferty, Yuan He, Joost Bekaert, Geert Vanderberghe

JM3, Vol. 14, Issue 03, 031216, (September 2015) https://doi.org/10.1117/12.10.1117/1.JMM.14.3.031216

KEYWORDS: Dysprosium, Photomasks, Immersion lithography, Source mask optimization, Optical proximity correction, Printing, Optical lithography, Visualization, Lens design, Directed self assembly

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Proceedings Article | 19 March 2015 Paper

Directed self-assembly (DSA) grapho-epitaxy template generation with immersion lithography

Yuansheng Ma, Junjiang Lei, J. Torres, Le Hong, James Word, Germain Fenger, Alexander Tritchkov, George Lippincott, Rachit Gupta, Neal Lafferty, Yuan He, Joost Bekaert, Geert Vanderberghe

Proceedings Volume 9423, 942306 (2015) https://doi.org/10.1117/12.2085850

KEYWORDS: Photomasks, Optical proximity correction, Printing, Source mask optimization, Optical lithography, Neodymium, Visualization, Transmission electron microscopy, Dysprosium, Directed self assembly

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Proceedings Article | 18 March 2015 Paper

Full chip two-layer CD and overlay process window analysis

Rachit Gupta, Shumay Shang, John Sturtevant

Proceedings Volume 9427, 94270H (2015) https://doi.org/10.1117/12.2086368

KEYWORDS: Metals, Overlay metrology, Error analysis, Manufacturing, Photomasks, Model-based design, Critical dimension metrology, Etching, Semiconducting wafers, Yield improvement

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Proceedings Article | 16 March 2015 Paper

Implementation of assist features in EUV lithography

Fan Jiang, Martin Burkhardt, Ananthan Raghunathan, Andres Torres, Rachit Gupta, James Word

Proceedings Volume 9422, 94220U (2015) https://doi.org/10.1117/12.2085946

KEYWORDS: SRAF, Photovoltaics, Extreme ultraviolet, Printing, Extreme ultraviolet lithography, Photomasks, Finite-difference time-domain method, Image quality, Metals, 3D modeling

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Proceedings Article | 23 March 2011 Paper

Influence of the illumination source on model-based SRAF placement

Rachit Gupta, Aasutosh Dave, Edita Tejnil, Srividya Jayaram, Pat LaCour

Proceedings Volume 7973, 79731U (2011) https://doi.org/10.1117/12.879492

KEYWORDS: SRAF, Model-based design, Source mask optimization, Logic, Resolution enhancement technologies, Image analysis, Optical lithography, Lithographic illumination, Lithography, Standards development

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Showing 5 of 13 publications

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