DRAM chip space is mainly determined by the size of the memory cell array patterns which consist of periodic memory cell features and edges of the periodic array. Resolution Enhancement Techniques (RET) are used to optimize the periodic pattern process performance. Computational Lithography such as source mask optimization (SMO) to find the optimal off axis illumination and optical proximity correction (OPC) combined with model based SRAF placement are applied to print patterns on target. For 20nm Memory Cell optimization we see challenges that demand additional tool competence for layout optimization. The first challenge is a memory core pattern of brick-wall type with a k1 of 0.28, so it allows only two spectral beams to interfere. We will show how to analytically derive the only valid geometrically limited source. Another consequence of two-beam interference limitation is a ”super stable” core pattern, with the advantage of high depth of focus (DoF) but also low sensitivity to proximity corrections or changes of contact aspect ratio. This makes an array edge correction very difficult. The edge can be the most critical pattern since it forms the transition from the very stable regime of periodic patterns to non-periodic periphery, so it combines the most critical pitch and highest susceptibility to defocus. Above challenge makes the layout correction to a complex optimization task demanding a layout optimization that finds a solution with optimal process stability taking into account DoF, exposure dose latitude (EL), mask error enhancement factor (MEEF) and mask manufacturability constraints. This can only be achieved by simultaneously considering all criteria while placing and sizing SRAFs and main mask features. The second challenge is the use of a negative tone development (NTD) type resist, which has a strong resist effect and is difficult to characterize experimentally due to negative resist profile taper angles that perturb CD at bottom characterization by scanning electron microscope (SEM) measurements. High resist impact and difficult model data acquisition demand for a simulation model that hat is capable of extrapolating reliably beyond its calibration dataset. We use rigorous simulation models to provide that predictive performance. We have discussed the need of a rigorous mask optimization process for DRAM contact cell layout yielding mask layouts that are optimal in process performance, mask manufacturability and accuracy. In this paper, we have shown the step by step process from analytical illumination source derivation, a NTD and application tailored model calibration to layout optimization such as OPC and SRAF placement. Finally the work has been verified with simulation and experimental results on wafer.
Electron multi-beam mask writers address the challenge of long mask write times for increasingly complex masks. The writing speed of the IMS multi-beam mask writer under consideration here depends on the data path and blanking device speed provided for exposing the patterns. It was initially believed that the maximum dose required for exposing the patterns could also be a limiting factor. We present a proximity effect correction scheme that improves image quality (compared to a dose-only correction) and allows for a maximum dose limit. We test this scheme with and without maximum dose limit, and compare the achieved image quality against that for a dose-only correction. The results of this simulation study are verified by comparing top down SEM images of resist structures from exposures using the different corrections.
KEYWORDS: Point spread functions, Cadmium, Data modeling, Error analysis, 3D modeling, Critical dimension metrology, Geometrical optics, Virtual reality, Electron beam direct write lithography, Model-based design
We demonstrate a flow for e-beam proximity correction (EBPC) to e-beam direct write (EBDW) wafer manufacturing
processes, demonstrating a solution that covers all steps from the generation of a test pattern for (experimental or virtual)
measurement data creation, over e-beam model fitting, proximity effect correction (PEC), and verification of the results.
We base our approach on a predictive, physical e-beam simulation tool, with the possibility to complement this with
experimental data, and the goal of preparing the EBPC methods for the advent of high-volume EBDW tools.
As an example, we apply and compare dose correction and geometric correction for low and high electron energies on
1D and 2D test patterns. In particular, we show some results of model-based geometric correction as it is typical for the
optical case, but enhanced for the particularities of e-beam technology.
The results are used to discuss PEC strategies, with respect to short and long range effects.
The continual shrinking of design rules as the industry follows Moore's Law and the associated need for low k1
processes, have resulted in more layout configurations becoming difficult to print within the required tolerances. OPC
recipes have needed to become more complex as tolerances decreased and acceptable corrections harder to find with
simple algorithms. With this complexity comes the possibility of coding errors and ensuring the solutions are truly
general. OPC Verification tools can check the quality of a correction based on pre-determined specifications for CD
variation, line-end pullback and Edge Placement Error and then highlight layout configuration where violations are
The problem facing a Mask Tape-Out group is that they usually have little control over the Design Styles coming in.
Different approaches to eliminating problematic layouts have included highly restrictive Design Rules , whereby
certain pitches or orientations are disallowed. Now these design rules are either becoming too complex or they overly
restrict the designer from benefiting from the reduced pitch of the new node. The tight link between Design and Mask
Tape-Out found in Integrated Device Manufacturers  (IDMs) i.e. companies that control both design and
manufacturing can do much to dictate manufacturing friendly layout styles, and push ownership of problem resolution
back to design groups. In fact this has been perceived as such an issue that a new class of products for designers that
perform Lithographic Compliance Check on design layout is an emerging technology . In contrast to IDMs,
Semiconductor Foundries are presented with a much larger variety of design styles and a set of Fabless customers who
generally are less knowledgeable in terms of understanding the impact of their layout on manufacturability and how to
The robustness requirements of a foundry's OPC correction recipe, therefore needs to be greater than that for an IDM's
tape-out group. An OPC correction recipe which gives acceptable verification results, based solely on one customer
GDS is clearly not sufficient to guarantee that all future tape-outs from multiple customers will be similarly clean. Ad
hoc changes made in reaction to problems seen at verification are risky, while they may solve one particular layout issue
on one product there is no guarantee that the problem may simply shift to another configuration on a yet to be
manufactured part. The need to re-qualify a recipe over multiple products at each recipe change can easily results in
excessive computational requirements. A single layer at an advanced node typically needs overnight runs on a large
processor farm. Much of this layout, however, is extremely repetitive, made from a few standard cells placed tens of
thousands of times.
An alternative and more efficient approach, suggested by this paper as a screening methodology, is to encapsulate the
problematic structures into a programmable test structure array. The dimensions of these test structures are
parameterized in software such that they can be generated with these dimensions varied over the space of the design
rules and conceivable design styles. By verifying the new recipe over these test structures one could more quickly gain
confidence that this recipe would be robust over multiple tape-outs. This paper gives some examples of the
implementation of this methodology.
Ability to predict process behavior under defocus has until now relied on explicit calculations, which while accurate, cannot be realistically used in full-chip optical and process correction strategies due to the long run times. In this work, we have applied a vector model for the optics, and a compact model for the resist development process. Simulations with these models are fast enough to be the basis of full-chip OPC. We verify this strategy with an independent set of measurements, and compare it to current lithographic process fitting strategies. The results indicate that by describing optical processes as accurately as possible, the model accuracy improves over a wider range of defocus conditions when compared to the traditional calibration method. As long as the calibration process successfully decouples optical and resist effects, relatively simple resist models deliver excellent accuracy within the noise level of the metrology measurements. Our data are based on one-dimensional and two-dimensional results using a 193nm system using 0.75 NA and off axis illumination with 6% attenuated phase shift mask. In all cases, a wide variety of sub-resolution assist feature rules were used in order to further test the ability of the models to predict various optical and resist environments.
Sub-Resolution Assists Features (SRAF) is a well known and well described method for process window improvement. The introduction of such a technique is not always an easy task for two reasons. On one hand the SRAF placement rules must be defined very well and on the other hand an empirical resist model must be created, which describes the process. Model based Optical and Process effects correction (MB-OPC) is using an empirical model so called black box, which must be able to predict properly the printing feature for any kind of complex design configuration. When SRAF are implemented in the design, the degree of freedom for the MB-OPC can be reduced. Beside that effort to predetermine as required as possible the target layer, SRAF placement rules and SRAF printing restrictions will limit the OPC. MB-OPC has to cover both the parameters space corresponding to areas in which SRAF are placed and the parameter space for which no SRAF has been implemented. Of course, it could also be possible to apply the correction of the proximity effect of a complex design with SRAF by an extensive rule-based OPC. Nevertheless the advantage of MB-OPC exists in the possibility to verify the design after Data Preparation by simulating it with the help of the calibrated model. However one should not trust the simulation alone, always a verification of the design on silicon would be necessary, by comparing simulation to SEM images. Beside the advantages of MB-OPC also weaknesses exist in the meantime, which could require a combination of rule-based and model-based OPC, so called “hybrid OPC”. Empirical models are very often only able to predict the proximity behavior due to a certain range, which is called the optical range of a model. Distances bigger than this range will be covered by extrapolations. This procedure would be correct, if the proximity behavior was as constant as in the area inside the optical range. We generated an empirical model with the Calibre Workbench from Mentor Graphics. For the model calibration we chose structures with SRAF placement rules, which we applied to the design as well as SRAF placement rules which were not applied to the design. Afterwards, we performed simulations of critical lines over pitch including SRAF. Beside the MB-OPC, we will also describe in this paper the process steps how to generate the SRAF placement rules. The restrictions resulting from the SRAF rules are presented. Subsequently, the experimental results will show that both for symmetrical and asymmetrical structures an improvement of the process window has been obtained. Also weaknesses become clear, which place either the model or the SRAF rule-set questionable. Finally two solutions will be compared, a pure MB-OPC including the isolated lines outside of the optical range and a combination of MB-OPC with a rule-based OPC table for the isolated lines.
Critical features of a product layout like isolated structures and complicated two-dimensional situations including line ends have often a smaller process window compared to regular highly nested features. It has been observed that the application of optical proximity corrections (OPC) can create yet more aggressive layout situations. Although corrected layouts meet the target contour under optimal exposure conditions, the process window of these structures under non-optimal conditions is thereby potentially reduced. This increases the risk of shorts and opens in the resist images of the designs under non-optimal exposure conditions. The requirement from a lithographer's point of view is to conduct a correction that considers the process window aspect besides the desired target contour. The present study investigates a concept of using the over-dose and under-dose responses of the simulated image of an exposed structure to optimize the correction value. The simulations describing the lithographic imaging process are based on an enhanced variable threshold model (VTRE). The placement error of the simulated edge of a structure is usually corrected for the nominal dose and focus settings. In the new concept the effective edge placement error is defined as the average of the edge placement errors for the over-dose and the edge placement error for the under-dose conditions. If a specific layout has a very non-symmetric response to over-/under exposure for the evaluated condition, it is prone to a certain failure mechanism (open or short). Hence calculating the average of the edge placement errors will shift the effective correction towards a layout with larger process window. The paper evaluates this concept for 100 nm ground rules and 193 nm lithography conditions. Examples of corrected layouts are presented together with experimental data. The limitations of the approach are discussed.
Optical proximity correction is one of the major hurdles chip manufacturing has to overcome. The paper presents evaluation results of CAPROX OPC, a rule based OPC software. Mask making influences as well as production requirements are discussed. Rule generation, one of the most critical parts in a rule based correction scheme is discussed. Two different applications are presented.
A hierarchical rule based optical proximity effect correction approach is presented. The approach has been driven by maskmaking and production requirements to make OPC a practical problem solution. The model based rule generation is presented, as well as benchmark tests on different state-of- the-art test chips.