Die-to-Model (D2M) inspection is an innovative approach to running inspection based on a mask design layout data. The
D2M concept takes inspection from the traditional domain of mask pattern to the preferred domain of the wafer aerial
image. To achieve this, D2M transforms the mask layout database into a resist plane aerial image, which in turn is
compared to the aerial image of the mask, captured by the inspection optics.
D2M detection algorithms work similarly to an Aerial D2D (die-to-die) inspection, but instead of comparing a die to
another die it is compared to the aerial image model. D2M is used whenever D2D inspection is not practical (e.g., single
die) or when a validation of mask conformity to design is needed, i.e., for printed pattern fidelity. D2M is of particular
importance for inspection of logic single die masks, where no simplifying assumption of pattern periodicity may be
done. The application can tailor the sensitivity to meet the needs at different locations, such as device area, scribe lines
In this paper we present first test results of the D2M mask inspection application at a mask shop. We describe the
methodology of using D2M, and review the practical aspects of the D2M mask inspection.
Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next
generation technology from development into production. High volume production in mask shops and wafer fabs
demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast
turnaround of reticle repair and defect disposition (W. Chou et al 2007).
Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution
inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution
mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the
mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI
can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically,
minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to
defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane.
This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced
reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results
from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all
the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI
are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between
WPI and AIMS<sup>TM</sup>.
Deep ultraviolet (DUV) femtosecond-pulsed laser ablation has numerous highly desirable properties for subtractive photomask defect repair. These qualities include high removal rates, resolution better than the focused spot size, minimized redeposition of the ablated material (rollup and splatter), and a negligible heat affected zone. The optical properties of the photomask result in a broad repair process window because the absorber film (whether Cr or MoSi) and the transmissive substrate allow for a high degree of material removal selectivity. Repair results and process parameters from such a system are examined in light of theoretical considerations. In addition, the practical aspects of the operation of this system in a production mask house environment are reviewed from the standpoint of repair quality, capability, availability, and throughput. Focus is given to the benefit received by the mask shop, and to the technical performance of the system.
To reduce the risk of EUV lithography adaptation for the 32nm technology node in 2009, Intel has operated a EUV mask Pilot Line since early 2004. The Pilot Line integrates all the necessary process modules including common tool sets shared with current photomask production as well as EUV specific tools. This integrated endeavor ensures a comprehensive understanding of any issues, and development of solutions for the eventual fabrication of defect-free EUV masks. Two enabling modules for "defect-free" masks are pattern inspection and repair, which have been integrated into the Pilot Line. This is the first time we are able to look at real defects originated from multilayer blanks and patterning process on finished masks over entire mask area.
In this paper, we describe our efforts in the qualification of DUV pattern inspection and electron beam mask repair tools for Pilot Line operation, including inspection tool sensitivity, defect classification and characterization, and defect repair. We will discuss the origins of each of the five classes of defects as seen by DUV pattern inspection tool on finished masks, and present solutions of eliminating and mitigating them.
The introduction of extreme ultraviolet (EUV) lithography into high volume manufacturing requires the development of a new mask technology. In support of this, Intel Corporation has established a pilot line devoted to encountering and eliminating barriers to manufacturability of EUV masks. It concentrates on EUV-specific process modules and makes use of the captive standard photomask fabrication capability of Intel Corporation. The goal of the pilot line is to accelerate EUV mask development to intersect the 32nm technology node. This requires EUV mask technology to be comparable to standard photomask technology by the beginning of the silicon wafer process development phase for that technology node. The pilot line embodies Intel's strategy to lead EUV mask development in the areas of the mask patterning process, mask fabrication tools, the starting material (blanks) and the understanding of process interdependencies. The patterning process includes all steps from blank defect inspection through final pattern inspection and repair. We have specified and ordered the EUV-specific tools and most will be installed in 2004. We have worked with International Sematech and others to provide for the next generation of EUV-specific mask tools. Our process of record is run repeatedly to ensure its robustness. This primes the supply chain and collects information needed for blank improvement.
Extreme Ultraviolet Lithography (EUVL) reflective mask blank development includes low thermal expansion material fabrication, mask substrate finishing, reflective multi-layer (ML) and capping layer deposition, buffer (optional)/absorber stack deposition, EUV specific metrology, and ML defect inspection. In the past, we have obtained blanks deposited with various layer stacks from several vendors. Some of them are not commercial suppliers. As a result, the blank and patterned mask qualities are difficult to maintain and improve. In this paper we will present the evaluation results of the EUVL mask pattering processes with the complete EUVL mask blanks supplied by the commercial blank supplier. The EUVL mask blanks used in this study consist of either quartz or ULE substrates which is a type of low thermal expansion material (LTEM), 40 pairs of molybdenum/silicon (Mo/Si) ML layer, thin ruthenium (Ru) capping layer, tantalum boron nitride (TaBN) absorber, and chrome (Cr) backside coating. No buffer layer is used. Our study includes the EUVL mask blank characterization, patterned EUVL mask characterization, and the final patterned EUVL mask flatness evaluation.
In this work, we are reporting on a lithography-based methodology and automation in the design of Program Defect masks (PDM’s). Leading edge technology masks have ever-shrinking primary features and more pronounced model-based secondary features such as optical proximity corrections (OPC), sub-resolution assist features (SRAF’s) and phase-shifted mask (PSM) structures. In order to define defect disposition specifications for critical layers of a technology node, experience alone in deciding worst-case scenarios for the placement of program defects is necessary but may not be sufficient. MEEF calculations initiated from layout pattern data and their integration in a PDM layout flow provide a natural approach for improvements, relevance and accuracy in the placement of programmed defects. This methodology provides closed-loop feedback between layout and hard defect disposition specifications, thereby minimizing engineering test restarts, improving quality and reducing cost of high-end masks. Apart from SEMI and industry standards, best-known methods (BKM’s) in integrated lithographically-based layout methodologies and automation specific to PDM’s are scarce. The contribution of this paper lies in the implementation of Design-For-Test (DFT) principles to a synergistic interaction of CAD Layout and Aerial Image Simulator to drive layout improvements, highlight layout-to-fracture interactions and output accurate program defect placement coordinates to be used by tools in the mask shop.