The method to perform Optical Proximity Correction (OPC) model calibration with contour-based input data from both small field of view (SFoV) and large field of view (LFoV) e-beam inspection is presented. For advanced OPC models - such as Neural Network Assisted Models (NNAM) , pattern sampling is a critical topic, where pattern feature vectors utilized in model training, such as image parameter space (IPS) is critical to ensure accurate model prediction [2-5]. In order to improve the design space coverage, thousands of gauges with unique feature vector combinations might be brought into OPC model calibration to improve pattern coverage. The time and cost in conventional Critical Dimension Scanning Electron Microscope (CD-SEM) metrology to measure this large amount of CD gauges is costly. Hence, an OPC modeling solution with contourbased input has been introduced . Built on this methodology, a single inspection image and SEM contour can include a large amount of information along polygon edges in complex logic circuit layouts. Namely, a better feature vector coverage could be expected . Furthermore, much less metrology time is needed to collect the OPC modeling data comparing to conventional CD measurements. It is also shown that by utilizing large field 2D contours, which are difficult to characterize by CD measurements, in model calibration the model prediction of 2D features is improved. Finally, the model error rms of conventional SFoV modeling and LFoV contour modeling between SEM contours and simulation results are compared.
EUV lithography has enabled shrinking feature sizes up until iN7 using the current Ta-based mask absorber. As we explore next generation nodes, iN5 and beyond, the mask three dimensional (M3D) effects will have a significant impact at wafer level due to the mask architecture, and the oblique illumination angles [1-2]. In order to mitigate these effects, we explore the optical performance of two alternative mask absorber candidates; a High-k absorber and an attenuated phase shifting mask absorber (AttPSM) and compare them to the current Ta-based mask absorber. We evaluate and compare the mask absorbers for memory and logic layers by lithographic source-mask optimization (SMO) using Mentor’s pxSMO tool with ASML’s NXE3400B settings. For memory, contact-holes are simulated using dark-field mask whereas the pillars case is simulated with bright field mask to evaluate bright field as a mask option for EUV with alternative mask absorbers. For logic case, we test these absorbers on iN5 self-aligned block (SAB) layer . The self-aligned block layer is also simulated by adding sub-resolution assist features (SRAFs) to predict the insertion point of SRAFs for logic designs and see if new mask absorber material can reduce the need of SRAF insertion. SMO for memory case shows higher common depth of focus (cDOF) and lower edge placement error (EPE) for High-k absorber over the conventional TaBN mask absorber, whereas significant gain in normalized image log slope (NILS) is observed for the AttPSM absorber. The logic case also has better performance in terms of common depth of focus (cDOF), NILS, EPE mask error enhancement factor (MEEF) and process variation band (PV-band). Adding SRAF’s to iN5 SAB improves the PV-band and image shift through focus for all three cases.
In this work we are introducing a manufacturing flow for the SALELE Process in details. Starting with layout decomposition, where the drawn layer is decomposed into 4 Masks: 2 Metal-like Masks, and 2 Block-like Masks. Then each of these masks is subjected to Optical Proximity Correction (OPC) process, and here we explain more about the OPC recipe development for each mask. Then we introduce a verification flow that performs two levels of verifications: (a) Litho verification, where the litho fidelity of each mask is quantified based on image quality measurements. (b) Final Manufactured shapes verification vs. expected output. This work has been carried out on an N3 candidate layout designed by IMEC.