Dr. Rama Nand Singh
Research Staff Member
SPIE Involvement:
Author | Instructor
Publications (7)

Proceedings Article | 30 August 2005 Paper
Proc. SPIE. 5875, Novel Optical Systems Design and Optimization VIII
KEYWORDS: Polarization, Ray tracing, Coating, Birefringence, Thin films, Light valves, Prisms, Projection systems, Lenses, Reflection

Proceedings Article | 3 May 2004 Paper
Proc. SPIE. 5379, Design and Process Integration for Microelectronic Manufacturing II
KEYWORDS: Optical proximity correction, Resolution enhancement technologies, Semiconducting wafers, Photomasks, Image processing, Edge roughness, Optical lithography, Model-based design, Lithography, Image enhancement

Proceedings Article | 26 June 2003 Paper
Proc. SPIE. 5040, Optical Microlithography XVI
KEYWORDS: Optical proximity correction, Data modeling, Printing, Image processing, Visualization, Calibration, Binary data, Solids, Failure analysis, Process modeling

SPIE Journal Paper | 1 April 2002
JM3 Vol. 1 Issue 01
KEYWORDS: Photomasks, Optimization (mathematics), Reticles, Diffraction, Wavefronts, Algorithm development, Phase shifts, Tolerancing, Resolution enhancement technologies, Detection and tracking algorithms

Proceedings Article | 14 September 2001 Paper
Proc. SPIE. 4346, Optical Microlithography XIV
KEYWORDS: Photomasks, Optimization (mathematics), Reticles, Wavefronts, Algorithm development, Diffraction, Tolerancing, Resolution enhancement technologies, Detection and tracking algorithms, Phase shifts

Showing 5 of 7 publications
Course Instructor
SC889: Layout-Aware Circuit Analysis
This course is directed towards presenting a methodology to include layout effects on circuit analysis. DFM imposes embellishments on the layout to ensure manufacturability with acceptable yields. Traditional circuit analysis and effects of process variability are performed at the schematics level using models for process corners and may lead to excessive guardbanding. Circuit Analysis that is able to predict impact and sensitivity of layout modifications uses circuit simulators together with information derived from litho simulations and helps the designer to ascertain that the layout accompanying the design meets the manufacturability criteria.
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