Standard Model Based OPC is based on resist and after etch CD measurements. In the case of non-linear photo-etch bias due to the etch microloading effect two-dimensional configuration can be wrongly corrected by the OPC model and hence lead to possible Si bridging. This paper reports a geometrical model for the determination of potential bridging in silicon trench structures that depends on the proximity of neighboring features. The model shows a possibility to detect and correct the post OPC data base by taking into account the non-linear effect caused by the non linear etch microloading. This approach can at the end leave the OPC model with a more straightforward photo resist model (and prevent the need to recreate a new OPC model), awhile-adding additional step of correction just in the locations of killer
effects like bridging may occur.
Proc. SPIE. 5567, 24th Annual BACUS Symposium on Photomask Technology
KEYWORDS: Lithography, Optical lithography, Calibration, Atomic force microscopy, Scanning electron microscopy, 3D metrology, Line width roughness, Optical proximity correction, Line edge roughness, Standards development
This paper presents Line Edge Roughness (LER) characterization for Tower Semiconductor 0.13um Standard Logic technology with advanced OPC modeling. First the applicability of top-view CD-SEM and AFM for LER measurement of poly-Si transistor gate characterization is studied. Then the influence of aerial image contrast and the gradient of the photoactive component on LER is reviewed and the possibility of minimizing LER by optimizing process conditions is considered.
Finally the impact of LER on OPC model accuracy is reviewed. Model predictability with and without LER taken into account is compared.
In this paper the impact of photolithography simulations on the workflow for accomplishing Full Chip DRC verification was investigated. The potential for simulation to reliably replace trial and error was determined. Initially simulations were done for a poly-Si layer, using KLA’s PROLITH v8 tool, to predict printability of Full Chip DRC. The simulation results were then compared to actual printed features. Photo resist parameter calibration was determined to have significant impact on the accuracy of printed feature predictions. The benefits of using simulations in the DRC verification workflow was determined in terms of cycle time and mask set cost reductions.
The sensitivity of lithographic process window to global planarity of the inter metal dielectric layers is established in this work. The inter metal dielectric layers, between the metal layers, were prepared by utilizing the H<SUB>2</SUB>O<SUB>2</SUB>/SiH<SUB>4</SUB> chemistry known as the 'Advanced Planarity Layer (APL)'. Four degrees of global planarity were tested within the APL process window, utilizing different H<SUB>2</SUB>O<SUB>2</SUB> stabilization pressures. SEM cross sections were used to determine the degree of planarity in the CMOS product and at lithographic test structures. The lithographic process window and the effect of the stepper leveling system were defined for typical high and low topographies. The results how a strong link between the lithographic process window to degree of global planarity of the APL. Good global planarity enlarged depth of focus and energy latitude, allowing a wider lithographic process window. Also, in cases of improved APL planarity, the stepper leveling system had only a limited contribution to a lithographic process window. This control over the global planarity of the inter metal dielectric layers and the wide lithographic process window that results eliminate the need for CMP at 0.5 (mu) technology.