Time dependent performance degradation due to negative bias thermal instability (NBTI) is one of the most
important reliability concerns for deep nano scale regime VLSI circuits. Under worst case NBTI can degrade circuit
performance in terms of timing by more than 10% over a period of 3 years. Reliability decisions taken early in system
design can bring significant benefits in terms of design quality. The proposed approach deals with use of latches and
NBTI aware scheduling of DFG to overcome the timing violations caused by NBTI. The experimental results suggest
that it incurs a very low area overhead and no performance penalty. We propose an algorithm to schedule the DFG and
show results for some of the common filters like EW and AR.