Phase-shift mask (PSM) technology in combination with 193nm illumination remains a viable option for high
contrast imaging towards 45nm half-pitch applications. The advent of hyper NA (immersion) lithography increases the
imaging sensitivity towards the photomask properties, such as mask-induced polarization. In addition, the use of PSM
technology implies taking into account the inherent photomask topography effects for a balanced through pitch imaging. A
good quartz etch depth control of +/-1o through pitch is required for optimized wafer imaging [1]. Therefore, a new PSM
material stack was proposed based on a transparent etch stop layer (TESL) in order to meet the stringent phase depth
requirements beyond 65nm half-pitch [2]. This extra layer allows over-etching of the quartz, resulting in a good etch depth
linearity and uniformity.
This study examines the manufacturability and printability of TESL-based masks. We examine the effect of an
improved quartz etch depth linearity on the through-pitch process windows for a TESL-based alternating aperture (AA)PSM.
Moreover, due to the different stack of photomask material compared to a classical photomask blank, the impact on
printability is investigated by simulations, AIMS and wafer imaging. The image imbalance compensation by trench biasing
needs to be optimized for through-pitch process windows.
The actual depth and line width of the structures is systematically probed within the photomask field. Based
on photomask metrology data, rigorous electro-magnetic field simulations are compared to wafer prints, obtained on an
ASML XT1250Di ArF immersion scanner working with a 0.85NA projection lens and to AIMS results from Zeiss
AIMS fab 193i.
Furthermore, feature sizes on the order of the lithography wavelength induce photomask polarization effects in the
imaging path [3]. The degree of polarization is compared to the polarization behavior of a conventional PSM.
In summary, this study assesses the capability of TESL PSM towards the 65nm node through-pitch imaging.
KEYWORDS: Photomasks, Ions, Etching, Ion beams, Lithography, Molecules, Electron beams, Image resolution, Scanning electron microscopy, Signal to noise ratio
The efficacy of currently available repair techniques has been assessed for a wide variety of defect types encountered on advanced lithographic masks. Focused ion beam (FIB) with gas-assisted etching and deposition, electron beam induced chemical processing (EBIC), and atomic force microscope based nano-machining (RAVE) were among the different methodologies evaluated. Various types of optical phase-shifting masks for the 45nm lithographic node, as well as nano-imprint lithography (NIL) templates, were used as test vehicles. Defect imaging resolution, spatial process confinement, repair edge placement, end-pointing control, sample damage (undesired changes in topographic or optical properties), and future extendibility served as the primary metrics for gauging repair performance. The primary aim of this study was to provide a single "snapshot" in time of the current development status of each tool for the context of 45nm node mask repair specifications and by no means were there any expectations for a final solution to already be commercially available. However, the results obtained from these tests should provide useful feedback and information to help improve the learning cycle for the development of 45nm lithographic node mask repair systems.
Today novel RET solutions are gaining more and more attention from the lithography community that is facing new challenges in attempting to meet the new requirement of the SIA roadmap. Immersion, high NA, polarization, and mask topography, are becoming common place terminology as lithographers continue to explore these areas. Here with, we compare a traditional 6% MoSi based EAPSM reticle and a high transmission solution made of a SiON/Cr film stack. Insights into the manufacturability of high transmission material are provided. Test patterns have been analyzed to determine the overall impact of imaging performance when used with immersion scanners and polarized light. Some wafer results provide reliability of simulations, which are used to make further investigation on polarization and immersion effects.
Today novel RET solutions are gaining more and more attention from the lithography community that is facing new challenges in attempting to meet the new requirement of the SIA roadmap. Immersion, high NA, polarization, and mask topography, are becoming common place terminology as lithographers continue to explore these areas. Here with, we compare a traditional 6% MoSi based EAPSM reticle and a high transmission solution made of a SiON/Cr film stack. Insights into the manufacturability of high transmission material are provided. Test patterns have been analyzed to determine the overall impact of imaging performance when used with immersion scanners and polarized light. Some wafer results provide reliability of simulations, which are used to make further investigation on polarization and immersion effects.
Intensity imbalance between the 0 and π phase features of c:PSM cause gate CD control and edge placement problems. Strategies such as undercut, selective biasing, and combinations of undercut and bias are currently used in production to mitigate these problems. However, there are drawbacks to these strategies such as space CD delta through pitch, gate CD control through defocus, design rule restrictions, and reticle manufacturability. This paper investigates the application of an innovative films-based approach to intensity balancing known as the Transparent Etch Stop Layer (TESL). TESL, in addition to providing a host of reticle quality and manufacturability benefits, also can be tuned to significantly reduce imbalance. Rigorous 3D vector simulations and experimental data compare through pitch and defocus performance of TESL and conventional c:PSM for 65nm design rules.
Imprint lithography has been proposed as a low cost method for next generation lithography for the manufacturing of semiconductors for the 45nm node and below, as costs for traditional optical lithography, and EUV lithography escalate to new levels that may prohibit new semiconductor devices from ever coming to market. While this was the widely proposed use of this technology, a whole host of new areas can take advantage of this lower cost manufacturing technology also. The template enables imprinting all these devices. Template manufacturing and development is currently done along side of state of the art reticle manufacturing. While the dimensions of the 1X templates is significantly smaller than what is needed for optical lithography templates, the dimensions are on the same order as the optical assist features, scatter bars and serifs used today. We will show current capability of 1X templates for imprint applications that are available commercially today, for semiconductor and nanofabrication applications. The advantages on the wafer side for the adoption of imprint lithography is the simplification of processing, reduced capital costs and process control when integrated in the wafer fab. The adoption of imprint reduces the barrier of entry to state of the art resolution for many older existing fabs that cannot spend upwards of 30 million dollars on an immersion I-line cluster. In this paper we will explore not only the technical aspects of imprint lithography, but also the economic impact as well.
Imprint lithography has been proposed as a low cost method for next generation lithography for the manufacturing of semiconductors for the 45nm node and below, as costs for traditional optical lithography, and EUV lithography escalate to new levels that may prohibit new semiconductor devices from ever coming to market. While this was the widely proposed use of this technology, a whole host of new areas can take advantage of this lower cost manufacturing technology. MEMS devices that can be scaled to smaller dimensions, construction of nano-optical devices for OLED applications, biosensors, light dispersion gratings and many other types of devices in need of nanometer scale fabrication. The template enables imprinting all these devices. Template manufacturing and development is currently done along side of state of the art reticle manufacturing. While the dimensions of the 1X templates is significantly smaller than what is needed for optical lithography templates, the dimensions are on the same order as the optical assist features, scatter bars and serifs used today. We will show current capability of 1X templates for imprint applications that are available commercially today, for semiconductor and nanofabrication applications.
In order to reduce mask making costs and improve wafer printability it is advantageous to determine machine parameters that will create highest probability of successful mask yield and mask image at CD and inspection. Proper simulation of actual product database helps to define the optimum e-beam machine settings for maximum probable yield and best mask pattern including OPC structures. In this paper we study the basic capability of the Nu-Flare E-beam mask writer emulation taking into account mask processing effects such as PEB. Analysis of how well software emulates the actual PEC corrections applied in the mask writer is necessary in predicting proper initial and subsequent machine settings for optimum yield and OPC structure fidelity.
Comparisons of the Nu-Flare PEC emulation against actual mask PEC patterns on chrome masks are presented. Excellent agreement is found to experimental data when the PEC algorithm is modified to keep dose to the dense line pattern constant for any given setting of the eta PEC parameter.
It has been demonstrated that the write time for 50keV E-beam masks is a function of layout complexity including figure count, vertex count and total line edge. This study is aimed to improve model fitting by utilizing all the variables generated from CATS. A better correlation of R2 = 0.99 was achieved by including quadratic and interaction terms. The vertex model was then applied to estimate write time of various nano-imprint templates. Accuracy of the vertex model is much better than the numbers generated from E-beam tool software. A 90nm test layout was treated with a mask optimization (MO) algorithm. A 26% write time reduction was observed through shot count reduction. The advanced features of the new generation E-beam writing tool combined with mask layout optimization, allows the same level of mask cost even though the capital cost of the new tool set increased 25%.
Today the industry is filled with intensity-balanced c:PSM and much more focus is being placed on innovative approaches such as CPL (and in conjunction with IML for Contacts) and tunable transmission embedded attenuating phase shift mask (TT-EAPSM). Each approach has its own merits and demerits depending on the manufacturing strategy and lithography performance required. Currently the only commercially available photomask blanks are different chrome thickness binary and 6% attenuating blanks using molybdenum-silicide, making the accessibility to alternate transmissions much more challenging. This paper investigates the mask manufacturability of a tunable transmission embedded attenuating phase shift mask. New film materials that are used in the mask blank manufacture are modeled, deposited and characterized to determine its ability to meet performance requirements. Sputtering models, by rate and gas component, determines film stacks with tunable transmissions and thicknesses. Chemical durability, etch selectivity and thickness are a few parameters of the films that have been characterized to enhance the manufacturability and process reliability of the masks. Lithography simulation models using measured optical properties were developed and test masks that include actual device designs were fabricated. Analysis of CD variation, pattern fidelity and process margin was performed using 3D mask simulation to understand the impact on 65nm design rules. Feasibility and performance of tunable transmission photomasks for use in design and lithography are verified. Moreover, the mask manufacturability and lithography performance is compared to other enhancement techniques and their merits presented.
Various sources contribute to mask haze formation including: chemical residuals from mask cleaning, out-gassing from pellicle glue/materials, and contaminants from the scanner ambient. This joint work examines cleaning techniques for haze minimization and whether or not there is haze formation after continuous laser irradiation. Masks with various designs and different cleaning techniques were tested in an ideal environment, isolated from out-gassing or other possible contaminants from the fab environment. Masks with and without patterns were subjected to 40kJ, accumulated dose, of laser radiation to simulate a wafer fab environment. Ion Chromatography (IC) and other surface analytical techniques were used to check the surface condition of masks before and after laser exposure. No haze was found on masks through transmission and IC measurements, when the test chamber was N2 purged. This may suggest that new cleaning techniques have helped reduce chemical residuals on masks. It is less likely for haze to grow when masks are clean to an ionic level and when laser exposure occurs in an uncontaminated, purged environment.
This paper investigates possible solutions to intensity imbalance minimization for 65nm node application through rigorous vector simulations. It provides a strategic plan to select the right technology for AAPSM application. Technologies such as undercut, bias, combination of undercut and bias and use of a Transparent Etch Stop Layer (TESL) are compared. The study looks at the effect of through pitch, defocus, phase error and sidewall profile on space CD bias for the technologies mentioned to determine the set of conditions that would provide the best compromise between performance and manufacturability. Simulations indicate the use of TESL along with undercut would provide best compromise between manufacturability and performance. Simulation results show that performance can be improved considerably by optimizing phase target. The use of vertical side walls is sufficient if the purpose of simulation is to determine trends. For more accurate simulations it is suggested that the profile used in simulation be matched to profiles seen on manufactured AAPSM.
The lithography prognosticator of the early 1980’s declared the end of optics for sub-0.5μm imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k1. Several authors have recently discussed manufacturing imaging solutions for sub-0.3k1 and the integration challenges. The requirements stated in the ITRS roadmap for current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will continue further for aggressive imaging solutions. Lithography and more importantly “imaging solutions” are driven by economics. The technology might be extremely innovative and “fun”, however, if it's too expensive it may never see the light of scanner. The authors have investigated and compared the capability of high transmission mask technology and image process integration for the 45nm node. However, the results will be graded in terms of design, mask manufacturability, imaging performance and overall integration within a given process flow.
Long write times have been an industry wide concern regarding rising mask costs. The purpose of this study is to develop a simple model that can predict mask write time precisely, without an e-beam writer. With a good understanding of the trade-offs between design complexity and write time, mask makers can work with mask designers more closely to simplify design and minimize mask cost. This work compared several basic models including calculations based on write area with a fixed e-beam shot size, a software estimation with a pre-set exposure, and a mask stage settling time. Our proposed model uses a completely different approach to examine the correlation between layout complexity (vertices count, total line edge, figure, etc.) through a CATS layout segmentation and actual write time. It is found that write time is a strong function of layout figure, vertex count and total line edge. Errors between actual write time and estimated write time from the new model reduced from 7% on average on the current production software to 3%. Additionally, the new model can operate independent of the writer type and without fractured data being transferred onto a writer. Also provided are a few case studies to evaluate the interaction between write time and basic shape/OPC (optical proximity correction). Using a simple design shape and a better data snapping strategy can reduce write time up to 10 fold for applications in nano-imprint template manufacturing. Several strategies to reduce mask cost are proposed.
To accelerate the time-to-market of advanced photomasks, Photronics launched its 90nm program in spring 2003. The program included three learning cycles and a technology transfer phase. Both 90nm test masks and product masks from leading integrated device manufacturers (IDMs) and foundries were exercised through the cycles. Stringent success criteria were set based on a survey of leading customers’ requirements and the International Technology Roadmap for Semiconductors (ITRS). Hundreds of binary masks, embedded attenuated phase shift masks (EAPSMs), and alternating aperture phase shift masks (AAPSMs) were produced throughout the program. All targets were exceeded. This paper describes program success criteria, complexity of customer requirements, 90nm test vehicle design, and efforts on improving critical dimension (CD) uniformity and registration. Results in positive and negative chemically amplified resist (CAR) and tunable etching for AAPSM are shown. Details on AAPSM undercut optimization, intensity and CD imbalance are reported.
As feature sizes shrink, metrology tools are challenged to deliver higher precision. To meet the demands of the semiconductor industry it is critical to determine and eliminate erros induced by metrology tools. It is also critical to investigate error-inducing factors neglected in the past. Image rotation is regularly experienced on a CD SEM, however error induced by it is assumed to be negligible and neglected. Experience shows an inline SEM often has image rotation of as much as ±26.3% of the edge thickness. For the range of rotation often experienced, experimental data fits the theoretical model suggested. Current tool monitoring techniques rely on pitch accuracy to monitor the day to day performance of the tool. Pitch is also used for tool calibration. However, pitch measurements are not significantly affected by image rotation hence using pitch as a standard for CD SEM monitoring is inadequate when dealing wiht a rotated image.
Recently, interest in the use of scanning probe microscopes (SPM) for metrology applications has grown. SPM can provide detailed topographical maps of reticles and wafers from which much useful data can be extracted. For example, CD measurements very near the bottom of sidewalls can be determined. Sidewall angles can be measured non-destructively. Micro-trenching (micro-loading) in etched quartz features on APSM can be characterized, and quartz bumps can be volume mapped for accurate dose control on FIB repair tools. The main issue complicating the use of SPM for metrology is the effect of tip shape and tip wear on the measurement data. For example, features with nearly vertical surfaces, like sidewalls, can't be measured accurately with conical tips because SPM scans will actually measure the sidewall of the tip and not the feature. This study will qualitatively address the issues associated with tip shape effects and discuss methods being employed to reduce or eliminate them.
Metrology is essential to success in all manufacturing processes. In microlithography metrology techniques have begun to shift from optical to SEM. In this paper we compare the capabilities of the new Flux-Area optical technique and of SEM techniques. SEM measurement has been increasing in mask shops because of the higher resolution it provides, despite disadvantages including damage to masks, charging effects, and inability to operate with pellicles. Optical measurements of photomasks are preferred because they are performed with light, in transmission. The success of virtual stepper software, which uses optical images in simulating stepper output, has demonstrated that optical images contain sufficient information to predict the results of even subwavelength lithography. Flux-Area measurement allows optical instruments to accurately measure features as small as (lambda) /6, or 0.08 (mu) using visible light (Fiekowsky and Selassie, 1999). It also allows the measurement of Optical Dimensions. This is the width of a line defined by the flux of light it transmits to the objective lens. In this study Flux-Area measurements of linewidths and contact are compared to SEM measurements and DUV AIMS microscope images. Results show that Flux-Area measurements are linear down to the smallest lines and holes tested, 0.23 (mu) and 0.4(mu) respectively. Thus the Flux-Area technique provides a practical alternative to SEM for metrology on current and future generation photomasks.
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