A CMOS compatible single resist layer lift-off process for forming patterns on a substrate is described. Unlike in most other methods, an ion bombardment is employed here to harden the top of the resist leaving the sidewall of the resist unaffected. The resist is then treated to a low temperature O2 plasma etching process to achieve a T-shaped undercut profile. This process is found to be simple, repeatable and controllable. Resist profile with adjustable overhang length and the sidewalls of the resist profile with an almost T-shape could be achieved with the help of the process described in the current work. Such increased overhang length prevents metallization of the sidewalls of the resist, and thus facilitates more rapid removal of the resist during lift-off. The process starts from a patterned resist layer having vertical resist profile. It is then subjected to Ion bombardment to harden the top surface of the resist leaving the sidewalls unaffected. The ions are directed at sufficient dose and energy to cause the top of the resist mask to get hardened. Subsequently, the resist patterns are subjected to a low temperature isotropic plasma etching process resulting in an under-cut T-shaped resist profile. This process is highly suitable for MEMS application where metals like Cr, Au, Cu etc are frequently used but are difficult to dry etch.
In this paper, we propose a sequential probability ratio test based on a two parameter Weibull distribution for IC failures. The shape parameter of the Weibull distribution characterizes the decreasing, constant and the increasing failure rate regions in the bath tub model for ICs. The algorithm detects the operating region of the IC based on the observed failure times. Unlike the fixed-length test, the proposed algorithm due to its sequential nature uses the minimum average number of devices for the test for fixed error tolerances in the detection procedure. We find that the proposed test is on an average 96 percent more efficient than the fixed-length test. Our algorithm is shown to be highly robust to the variations in the model parameters unlike other existing sequential tests. Further, extensive simulations are used to validate the analytic results of the sequential test.
In this paper we describe the design and implementation of a systolic VLSI chip for computing scale space. The hardware can also be used for Gaussian filtering and Laplacian of Gaussian edge detection. The chip is based on an architecture proposed earlier. The algorithm and the architecture exploit a high degree of pipelining and parallelism in order to obtain high speed, efficiency, and throughput. The hardware organization of a processor cell is simple enough that the entire systolic array can be realized as a single chip system. A prototype CMOS VLSI chip implementing a single processor cell was designed, fabricated, and tested. Based on the estimates obtained from the prototype chip, a real life chip is expected to operate at a rate of 40 MHz. The chip can process a 512 X 512 gray-level image in about 0.006 seconds and a 1000 X 1000 gray-level image in 0.012 seconds which is much faster than other systems reported in the literature.