Optical Proximity Correction (OPC) is a compute-intensive process used to generate photolithography mask shapes at advanced VLSI nodes. Previously, we reported a modified two-step OPC flow which consists of a first pattern replacement step followed by a model based OPC correction step . We build on this previous work and show how this hybrid flow not only improves full chip OPC runtime, but also significantly improves mask correction consistency and overall mask quality. This is demonstrated using a design from the 20nm node, which requires the use of model based SRAF followed by model based OPC to obtain the full mask solution.
Overlay control is becoming increasingly more important with the scaling of technology. It has become even more critical and more challenging with the move toward multiple-patterning lithography, where overlay translates into CD variability. Design rules and overlay have strong interaction and can have a considerable impact on the design area, yield, and performance. We study this interaction and evaluate the overall design impact of rules, overlay characteristics, and overlay control options. For this purpose, we developed a model for yield loss from overlay that considers overlay residue after correction and the breakdown between field-to-field and within-field overlay; the model is then incorporated into a general design-rule evaluation framework to study the overlay/design interaction. The framework can be employed to optimize design rules and more accurately project overlay-control requirements of the manufacturing process. The framework is used to explore the design impact of litho-etch litho-etch double-patterning rules and poly line-end extension rule defined between poly and active layer for different overlay characteristics (i.e., within-field versus field-to-field overlay) and different overlay models at the 14-nm node. Interesting conclusions can be drawn from our results. For example, one result shows that increasing the minimum mask-overlap length by 1 nm would allow the use of a third-order wafer/sixth-order field-level overlay model instead of a sixth-order wafer/sixth-order field-level model with negligible impact on design.
Overlay control is becoming increasingly more important with the scaling of technology. It has become even more critical and more challenging with the move toward multiple-patterning lithography, where overlay translates into CD variability. Design rules and overlay have strong interaction and can have a considerable impact on the design area, yield, and performance. This paper offers a framework to study this interaction and evaluate the overall design impact of rules, overlay characteristics, and overlay control options. The framework can also be used for designing informed, design-aware overlay metrology and control strategies. In this work, The framework was used to explore the design impact of LELE doublepatterning rules and poly-line end extension rule defined between poly and active layer for different overlay characteristics (i.e., within-field vs. field-to-field overlay) and different overlay models at the 14nm node. Interesting conclusions can be drawn from our results. For example, one result shows that increasing the minimum mask-overlap length by 1nm would allow the use of a third-order wafer/sixth-order field-level overlay model instead of a sixth-order wafer/sixth-order field-level model with negligible impact on design.
Double patterning (DP) in a litho-etch-litho-etch (LELE) process is an attractive technique to scale the <i>K</i><sub>1</sub> factor below 0.25. For dense bidirectional layers such as the first metal layer (M1), however, density scaling with LELE suffers from
poor tip-to-tip (T2T) and tip-to-side (T2S) spacing. As a result, triple-patterning (TP) in a LELELE process has emerged
as a strong alternative. Because of the use of a third exposure/etch, LELELE can achieve good T2T and T2S scaling as
well as improved pitch scaling over LELE in case further scaling is needed. TP layout decomposition, a.k.a. TP coloring,
is much more challenging than DP layout decomposition. One of the biggest complexities of TP decomposition is that
a stitch can be between different two-mask combinations (i.e. first/second, first/third, second/third) and, consequently,
stitches are color-dependent and candidate stitch locations can be determined only during/after coloring. In this paper, we
offer a novel methodology for TP layout decomposition. Rather than simplifying the TP stitching problem by using DP
candidate stitches only (as in previous works), the methodology leverages TP stitching capability by considering additional
candidate stitch locations to give coloring higher flexibility to resolve decomposition conflicts. To deal with TP coloring
complexity, the methodology employs multiple DP coloring steps, which leverages existing infrastructure developed for
DP layout decomposition. The method was used to decompose bidirectional M1 and M2 layouts at 45nm, 32nm, 22nm,
and 14nm nodes. For reasonably dense layouts, the method achieves coloring solutions with no conflicts (or a reasonable
number of conflicts solvable with manual legalization). For very dense and irregular M1 layouts, however, the method was
unable to reach a conflict-free solution and a large number of conflicts was observed. Hence, layout simplifications for the
M1 layer may be unavoidable to enable TP for the M1 layer. Although we apply the method for TP, the method is more
general and can be applied for multiple patterning with any number of masks.
Techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits
are described. These results are from multi-discipline, collaborative university-industry research and emphasize
anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes
design and testing electronic monitors in silicon at 45 nm and
fast-CAD tools to identify systematic variations for entire
chip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppress
random variability components. The Design-for-Manufacturing research includes double pattern decomposition in the
presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and
speed, the extension of timing analysis methodology to capture across process-window effects and electrical processwindow
This paper proposes shift-trim double patterning lithography (ST-DPL), a cost-effective method for achieving 2× pitchrelaxation
with a single photomask (especially at polysilicon layer). The mask is re-used for the second exposure by
applying a translational mask-shift. Extra printed features are then removed using a non-critical trim exposure. The
viability of ST-DPL is demonstrated. The proposed method has many advantages with virtually no area overhead (< 0.3%
standard-cell area): (1) cuts mask-cost to nearly half that of standard-DPL, (2) reduces overlay errors between the two
patterns and can virtually eliminate it in some process implementations, (3) alleviates the bimodal problem in doublepatterning,
and (4) enhances throughput of first-rate scanners. We implement a small 45nm standard-cell library and small
benchmark designs with ST-DPL to illustrate its viability.
In double patterning lithography (DPL), overlay error between two patterning steps at the same layer translates into CD
variability. Since CD uniformity budget is very tight, overlay control becomes a tough challenge for DPL. In this paper,
we electrically evaluate overlay error for BEOL DPL with the goal of studying relative effects of different overlay sources
and interactions of overlay control with design parameters. Experimental results show the following: (a) overlay electrical
impact is not significant in case of positive-tone DPL (< 3.4% average capacitance variation) and should be the base for
determining overlay budget requirement; (b) when considering congestion, overlay electrical impact reduces in positivetone
DPL; (c) Design For Manufacturability (DFM) techniques like wire spreading can have a large effect on overlay
electrical impact (20% increase of spacing can reduce capacitance variation by 22%); (d) translation overlay has the largest
electrical impact compared to other overlay sources; and (e) overlay in y direction (x for horizontal metalization) has
negligible electrical impact and, therefore, preferred routing direction should be taken into account for overlay sampling
and alignment strategies.