Advancing technology nodes in DRAM continues to drive the reduction of on-product overlay (OV) budget. This gives rise to the need for OV metrology with greater accuracy. However, the ever increasing process complexity brings additional challenges related to metrology target deformation, which could contribute to a metrology error. Typically, an accurate OV measurement involves several engineering cycles for target and recipe optimization. In particular, process optimization in either technology development (TD) phase or high volume manufacturing (HVM) phase might influence metrology performance, which requires re-optimization. Therefore, a comprehensive solution providing accuracy and process robustness hereby minimizing the cycle time is highly desirable. In this work, we report multi-wavelength μDBO enhanced with accuracy aware pixel selection as a solution for robust OV measurement against process changes as well as improved accuracy in HVM. Accuracy aware pixel selection is capable of tackling intra-target processing variations and is established on a multi-wavelength algorithm with immunity to target asymmetry impact. DRAM use cases in FEOL critical layers will be discussed in this paper. Superior robustness and accuracy will be demonstrated together with improved on-product OV performance, promising a process of record metrology solution in specific applications throughout the TD and HVM.
Requirements for control of critical dimension (CD) become more demanding as the integrated circuit (IC) feature size specifications become tighter and tighter. Critical dimension control, also known as CDC, is a well-known laser-based process in the IC industry that has proven to be robust, repeatable, and efficient in adjusting wafer CD uniformity (CDU) [Proc. SPIE6152, 615225 (2006)]. The process involves locally and selectively attenuating the deep ultraviolet light which goes through the photomask to the wafer. The input data for the CDC process in the wafer fab is typically taken from wafer CDU data, which is measured by metrology tools such as wafer-critical dimension—scanning electron microscopy (CD-SEM), wafer optical scatterometry, or wafer level CD (WLCD). The CD correction process uses the CDU data in order to create an attenuation correction contour, which is later applied by the in-situ ultrashort laser system of the CDC to locally change the transmission of the photomask. The ultrashort pulsed laser system creates small, partially scattered, Shade-In-Elements (also known as pixels) by focusing the laser beam inside the quartz bulk of the photomask. This results in the formation of a localized, intravolume, quartz modified area, which has a different refractive index than the quartz bulk itself. The CDC process flow for improving wafer CDU in a wafer fab with detailed explanations of the shading elements formation inside the quartz by the ultrashort pulsed laser is reviewed.
Block co-polymer directed self-assembly (BCP DSA) has become an area of fervent research activity as a potential alternative or adjunct to EUV lithography or self-aligned pitch multiplication strategies. This presentation will evaluate two DSA strategies for patterning line-space arrays at 30nm pitch: graphoepitaxial DSA with surface-parallel cylinder BCPs and chemoepitaxial DSA with surface-normal lamellar BCPs. A comparison of pattern transfer into hard-mask and substrate films will be made by consideration of line and space CDs, line profile of cross-sectional SEM images, and comparison of relative LWR/SWR. The processes will be benchmarked against Micron’s process used in manufacturing its 16nm half-pitch NAND part.
Circuit layout and design rules have continued to shrink to the point where a few nanometers of pattern misalignment can negatively impact process capability and device yields. As wafer processes and film stacks have become more complex, overlay and alignment performance in high-volume manufacturing (HVM) have become increasingly sensitive to process and tool variations experienced by incoming wafers. Current HVM relies on overlay control via advanced process control (APC) feedback, single-exposure tool grid stability, scanner-to-scanner matching, correction models, sampling strategies, overlay mark design, and metrology. However, even with improvements to those methods, a large fraction of the uncorrectable errors (i.e., residuals) still remains. While lower residuals typically lead to increased yield performance, it is difficult to achieve in HVM due to the large combinations of wafer history in terms of prior tools, recipes, and ongoing process conversions. Hence, it is critical to understand the effect of residual errors on measurement sampling and model parameters to enable process control. In this study, we investigate the following: residual errors of sub-40nm processes as a function of correction models, sensitivity of the model parameters to residue, and the impact of data quality.
The need for lithographic tool advances for reducing feature size, pitch (low k1 processing), and improving overlay
stems directly from next generation circuit layout and performance roadmaps1. Overlay error or layer-to-layer
misalignment tolerances have continued to decrease to the point where a few nanometers of misalignment can seriously
impact process and device yields. In this work, we expand our previous work2 and introduce a new scanner aberration
monitoring methodology that can both measure and deconvolve lens distortion from scanning synchronization error
while simultaneously providing machine corrections for accurate tool matching. Experimental data taken from several
machines suggests it is possible to ameliorate scanning synchronization error for each machine and improve tool-to-tool
matching at the level required for next generation processing. Finally, we discuss applications of this new technology
including practical fab implementation and discovering problematic scanning tool signatures.