Extreme ultraviolet lithography (EUVL) is entering an industry production phase for 7nm logic and is under development for next node logic and memory applications. A key benefit of EUVL for logic interconnect lithography comes from the ability to pattern the metal layer at aggressive pitch using a single exposure. We report here a mask process compatible with a 30nm pitch patterning module for the demanding sub 7nm node, single expose interconnect application. We found a large increase in mask to wafer image transfer sensitivity during the 32nm to 30nm pitch shrink development that led to increases in stochastic and systematic wafer defect generation mechanisms. In this work, we describe our steps to characterize, model and improve the mask related factors that reduce this sensitivity as part of a successful 30nm pitch patterning module demonstration. High resolution wide area electron beam mask inspection alongside a suite of advanced mask characterization and optimization(AMCO)tools were key elements in understanding mask process gaps and improvement opportunities. Critical mask parameters optimized in closed loop with wafer response included two and three dimensional pattern fidelity, line roughness and spatial variability. Mask critical dimension targeting was found to be a critical factor for delivering the yielding 30nm pitch wafer process and this targeting was tuned dynamically through mask and wafer co-optimization. Finally, the role of wafer anchored process simulation proved an invaluable guide for linking various mask error source mechanisms to the wafer response.
Metrology of nanoscale patterns poses multiple challenges that range from measurement noise, metrology errors, probe size etc. Optical Metrology has gained a lot of significance in the semiconductor industry due to its fast turn around and reliable accuracy, particularly to monitor in-line process variations. Apart from monitoring critical dimension, thickness of films, there are multiple parameters that can be extracted from Optical Metrology models3. Sidewall angles, material compositions etc., can also be modeled to acceptable accuracy. Line edge and Line Width roughness are much sought of metrology following critical dimension and its uniformity, although there has not been much development in them with optical metrology. Scanning Electron Microscopy is still used as a standard metrology technique for assessment of Line Edge and Line Width roughness. In this work we present an assessment of Optical Metrology and its ability to model roughness from a set of structures with intentional jogs to simulate both Line edge and Line width roughness at multiple amplitudes and frequencies. We also present multiple models to represent roughness and extract relevant parameters from Optical metrology. Another critical aspect of optical metrology setup is correlation of measurement to a complementary technique to calibrate models. In this work, we also present comparison of roughness parameters extracted and measured with variation of image processing conditions on a commercially available CD-SEM tool.
Pattern transfer fidelity is always a major challenge for any lithography process and needs continuous improvement. Lithographic processes in semiconductor industry are primarily driven by optical imaging on photosensitive polymeric material (resists). Quality of pattern transfer can be assessed by quantifying multiple parameters such as, feature size uniformity (CD), placement, roughness, sidewall angles etc. Roughness in features primarily corresponds to variation of line edge or line width and has gained considerable significance, particularly due to shrinking feature sizes and variations of features in the same order. This has caused downstream processes (Etch (RIE), Chemical Mechanical Polish (CMP) etc.) to reconsider respective tolerance levels. A very important aspect of this work is relevance of roughness metrology from pattern formation at resist to subsequent processes, particularly electrical validity. A major drawback of current LER/LWR metric (sigma) is its lack of relevance across multiple downstream processes which effects material selection at various unit processes. In this work we present a comprehensive assessment of Line Edge and Line Width Roughness at multiple lithographic transfer processes. To simulate effect of roughness a pattern was designed with periodic jogs on the edges of lines with varying amplitudes and frequencies. There are numerous methodologies proposed to analyze roughness and in this work we apply them to programmed roughness structures to assess each technique’s sensitivity. This work also aims to identify a relevant methodology to quantify roughness with relevance across downstream processes.
We report on the printability, mitigation and actinic mask level review of programmed substrate blank pit and bump defects in a EUV lithography test mask. We show the wafer printing behavior of these defects exposed with an NXE:3300 EUV lithography scanner and the corresponding mask level actinic review using the AIMS<sup>TM</sup> tool. We will show which categories of these blank substrate defects print on wafer and how they can be mitigated by hiding these defects under absorber lines. Furthermore we show that actinic AIMS<sup>TM</sup> mask review images of these defects, in combination with a simple thresholded resist transfer model, can accurately predict their wafer printing profiles. We also compare mask level actinic AIMS<sup>TM</sup> to top down mask SEM review in their ability to detect these defects.
Over the past few years numerous advancements in EUV Lithography have proven its feasibility of insertion into High Volume Manufacturing (HVM).<sup>1, 2</sup> A lot of progress is made in the area of pellicle development but a commercially solution with related infrastructure is currently unavailable.<sup>3, 4</sup> Due to current mask structure and unavailability of a pellicle, a comprehensive strategy to qualify (native defects) and monitor (adder defects) defectivity on mask and wafer is required for implementing EUV Lithography in High Volume Manufacturing. In this work, we assess multiple strategies for mask and wafer defect inspection including a two-fold solution to leverage resolution of e-beam inspection along with throughput of optical inspection are evaluated. Defect capture rates for inspections based on full-die, critical areas based on priority and hotspots based on design and prior inspection data are evaluated. Each strategy has merits and de-merits, particularly related to throughput, effective die coverage and computational overhead. A production ready EUV Exposure tool was utilized to perform exposures at the IBM EUV Center of Excellence in Albany, NY for EUV Lithography Development along with a fully automated line of EUV Mask Infrastructure tools. We will present strategies considered in this study and discuss respective results. The results from the study indicate very low transfer rate of defect detection events from optical mask inspection. They also suggest a hybrid strategy of utilizing both optical and e-beam inspection can provide a comprehensive defect detection which can be employed in High Volume Manufacturing.
Native acting phase-programmed defects, otherwise known as buried program defects, with attributes very similar to native defects, were successfully fabricated using a high-accuracy overlay technique. The defect detectability and visibility were analyzed with conventional amplitude and phase-contrast blank inspection at 193-nm wavelength, pattern inspection at 193-nm wavelength, and scanning electron microscopy. The mask was also printed on wafer, and printability is discussed. Finally, the inspection sensitivity and wafer printability are compared, leading to the observation that the current blank- and pattern-inspection sensitivity is not enough to detect all of the printable defects.
As Extreme Ultraviolet (EUV) lithography has matured, numerous imposing technical challenges have been the focus of intense scrutiny, including the EUV radiation source, reflective optics, and fundamental mask fabrication. There has been a lurking question on the state of mask defectivity that has been almost unanswerable until the recent relative maturation of the rest of the infrastructure. Without readily available actinic blank or patterned inspection systems, EUV blank and mask manufacturers must continue to rely on relatively low resolution optical systems for blank characterization. Despite best efforts, detectable defects still exist; these can be classified into three types: small defects that can be avoided through pattern-shift, medium defects that can be repaired, and large defects which must be suppressed during manufacture. To successfully intercept high-volume-manufacturing (HVM) for the 7nm node, aggressive, continued industry focus is required to ensure that these three defect types are addressed. Without actinic mask inspection, an unknown element with EUV lithography continues to be the presence of nondetected printable defects – defects that print on wafer despite being undetected during mask or blank fabrication. Another risk is that until recently, focus has been on developing techniques to identify catastrophic defects, while past manufacturing experience tells us that much more subtle defects (<10% CD variation) can have significant impact on yield and performance. Using information from many characterization sources, including blank inspections, patterned inspection, atomic-force microscopy (AFM), scanning-electron microscopy (SEM), as well as 36nm and 32nm pitch wafer printing results, we will try to address what the real current state of mask defectivity is. We will discuss techniques to answer the key questions of: “What defects print, what defects do not, and what might our inspections methods be missing?” From this vantage point, we will analyze the current mask defectivity rates and sources, and assess the gap in capability to support full HVM support.
NAP-PD (Native Acting Phase – Programmed Defects), otherwise known as buried program defects, with attributes very similar to native defects, are successfully fabricated using a high accuracy overlay technique. The defect detectability and visibility are analyzed with conventional phase contrast blank inspection @193 nm wavelength, pattern inspection @193 nm wavelength and SEM. The mask is also printed on wafer and printability is discussed. Finally, the inspection sensitivity and wafer printability are compared, leading to the observation that the current blank and pattern inspection sensitivity is not enough to detect all of the printable defects.
The backside of photomasks have been largely ignored during the last several decades of development, with the exception of avoiding gross damage or defects, as almost all problems are far enough out of the focal plane to have minimal effect on imaging. Since EUV masks are reflective, and the column is held in a vacuum, scanners have been designed to utilize electrostatic chucking. With the chucking system for EUV, the requirements for the backside of the mask must be redefined to integrate concerns in substrate design, mask manufacturing, and usage. The two key concerns with respect to an electrostatic chuck are defects and durability. Backside defects can affect imaging, while potentially damaging or contaminating the tool, the mask, or even subsequently used masks. Compromised durability, from either usage or cleaning, can affect the ability of the chuck to hold the mask in place. In this study, these concerns are evaluated in three stages: minimizing defects created during mask fabrication, actions taken upon discovery of defects, and durability of the backside film with continued cleans and chucking. Data incorporated in this study includes: sheet resistance, film thickness, and optical inspection images. Incorporating the data from the three stages of fabrication, disposition, and lifetime will help us define how to structure backside EUV mask handling during mask manufacture and indicate what further solutions are needed as EUV technology transitions into manufacturing.
The detection of EUV mask adder defects has been investigated with an optical wafer defect inspection system employing a methodology termed Die-to-“golden” Virtual Reference Die (D2VRD). Both opaque and clear type mask absorber programmed defects were inspected and characterized over a range of defect sizes, down to (4x mask) 40 nm. The D2VRD inspection system was capable of identifying the corresponding wafer print defects down to the limit of the defect printability threshold at approximately 30 nm (1x wafer). The efficacy of the D2VRD scheme on full chip wafer inspection to suppress random process defects and identify real mask defects is demonstrated. Using defect repeater analysis and patch image classification of both the reference die and the scanned die enables the unambiguous identification of mask adder defects.
The black border is a frame created by removing all the multilayers on the EUV mask in the region
around the chip. It is created to prevent exposure of adjacent fields when printing an EUV mask on a
wafer. Papers have documented its effectiveness. As the technology transitions into
manufacturing, the black border must be optimized from the initial mask making process through its
life. In this work, the black border is evaluated in three stages: the black border during fabrication,
the final sidewall profile, and extended lifetime studies.
This work evaluates the black border through simulations and physical experiments. The simulations
address concerns for defects and sidewall profiles. The physical experiments test the current black
border process. Three masks are used: one mask to test how black border affects the image
placement of features on mask and two masks to test how the multilayers change through extended
cleans. Data incorporated in this study includes: registration, reflectivity, multilayer structure images
and simulated wafer effects.
By evaluating the black border from both a mask making perspective and a lifetime perspective, we
are able to characterize how the structure evolves. The mask data and simulations together predict
the performance of the black border and its ability to maintain critical dimensions on wafer. In this
paper we explore what mask changes occur and how they will affect mask use.
EUV Lithography is aimed to be inserted into mainstream production for sub-20nm pattern fabrication. Unlike conventional optical lithography, frequent defectivity monitors (adders, repeaters etc.) are required in EUV lithography. Due to sub-20nm pattern and defect dimensions e-beam inspection of critical pattern areas is essential for yield monitor. In previous work we showed sub-10nm defect detection sensitivity<sup>1</sup> on patterned resist wafers. In this work we report 8-10× improvement in scan rates of etched patterns compared to resist patterns without loss in defect detection sensitivity. We observed good etch transfer of sub-10nm resist features. A combination of smart scan strategies with improved etched pattern scan rates can further improve throughput of e-beam inspection. An EUV programmed defect mask with Line/Space, Contact patterns was used to evaluate printability of defects and defect detection (Die-Die and Die-Database) capability of the e-beam inspection tool. Defect inspection tool parameters such as averaging, threshold value were varied to assess its detection capability and were compared to previously obtained results on resist patterns.
Scatterometry is one of the most useful metrology methods for the characterization and control of critical dimensions and the detailed feature shape of periodic structures found in the microelectronics fabrication processes. Spectroscopic ellipsometry (SE) and normal incidence reflectometry (NI)-based scatterometry are widely used optical methodologies for metrology of these structures. Evolution of improved optical hardware and faster computing capabilities led to the development of Mueller matrix (MM)-based scatterometry (MMS). Unlike SE and NI, MM data provides complete information about the optical reflection and transmission of polarized light interacting with a sample. This gives MMS an advantage over traditional SE scatterometry due to the ability to characterize samples that have anisotropic optical properties and depolarize light. In this paper, we present the study of full MM (16-element) scatterometry over a wide spectral range from 245 to 1700 nm on a series of one-dimensional, two-dimensional symmetric, and asymmetric grating structures. A series of laterally complex nanoscale structures were designed and fabricated using a state-of-the-art e-beam patterning. Spectroscopic MM and SE data were collected using a dual rotating compensator ellipsometer. Commercial modeling software based on the rigorous coupled-wave approximation was used to precisely calculate the critical dimensions. Results from MMS were compared with scanning electron microscopy.
At the end of 2008, the College of Nanoscale Science and Engineering (CNSE) formally accepted a Vistec VB300
Gaussian electron beam lithography system. The system is a key component of the overall lithography strategy of the
College and complements existing state of the art tooling for 193nm immersion, Extreme Ultra Violet and nanoimprint.
The demonstrated resolving power of the system easily exceeds that of the facility's optical scanners. Together with
300mm wafer compatibility, and a class 1 mini environment, the system is well poised to execute its primary mission of
supporting a variety of programs in post CMOS device integration. For a 300mm tool to be able to exchange wafers
with other tooling in a full flow line it is necessary to pass stringent backside metal contamination testing. TXRF (total
reflection x-ray fluorescence) testing performed with 300mm wafers on the VB300 satisfied the permitted metal
contamination levels and cleared the way for introduction of ebeam patterned wafers into the process flow. Most of the
tooling in the 300mm line handles wafers in front opening universal pods (FOUPS). With the relatively low throughput
of the system (hours per wafer, not wafers per hour), this type of interface is not required. In order to maintain a low
level of defects, 300mm wafers are removed from the FOUPS in the class 1 mini environment and loaded into the
In addition to the 300mm capability, the system supports a wide range of wafer sizes, photomasks and piece parts. This
enables the platform to support the 200mm activities at the College as well as the small samples frequently encountered
with novel materials that have no support tooling available for 200mm and 300mm wafer sizes.
The VB300 platform readily met the Vistec standard acceptance test specifications. The paper presents details of the acceptance test together with examples of additional work in progress that includes implementation of rigorous tool monitor standards, imprint template fabrication and mix and match overlay between the VB300 and optical patterning tools.