In contrast to defect limited yield loss, systematic yield detractors like lithography hotspots may cause a huge yield loss
per event. For 45 nm and subsequent technology nodes, those findings are for this reason classified as DRC-like errors
and need to be fixed before tape-out. In this paper, we report a comparison - from the use-model point-of-view - of two
different methods for removal of lithography hotspots. First, a rip-up & re-routing and second, a guided-repair approach
will be presented. This includes a discussion of the impact in the routing context, mainly radius of influence and timing
closure, aspects of multiple layer involvement and the layout hierarchy, and the limitations caused by the layout grid.
Particle induced defects are still one of the major sources of yield loss in semiconductor manufacturing. In addition, optical distortion of shapes cannot be ignored in modern technologies and requires increasing design effort in order to avoid yield loss and minimize manufacturing costs. Although suppliers of automated routing tools are increasingly addressing these issues, we still see significant improvement potential even in layouts produced by routers attributed as DfM aware. We propose a post-routing clean-up step to address both defect and lithography related yield loss in the routing layers. In contrast to a "find and fix" approach, this methodology creates lithography friendly layout "by construction", based on the general concept of shape simplification and standardization.
With the upcoming technology generations, it will become increasingly challenging to provide a good yield and/or yield
ramp. In addition, we observe yield detractors migrating from defects via systematic effects such as litho and CMP to
out-of-spec scenarios, i.e. a slow, but continuous migration into an typical environment for analog devices. Preparing for
such scenarios, worldwide activities are ongoing to extract the device parameters not from the drawn layout, but from the
resist image or, at best, from etched contours. The litho-aware approach allows to detect devices of high variability and
to reduce the variations on the critical paths based on this analysis. We report in this paper the analysis of MOSFET
parameters from printed PC contours of standard cell libraries based on litho simulation (LfD). It will be shown how to
extract gate lengths and -widths from print images, how to backannotate the gate parameters into a litho-aware spice
netlist and to finally analyse the effect of across chip line width variations (ACLV) and process window influence based
on litho-aware spice netlist.
Proc. SPIE. 6521, Design for Manufacturability through Design-Process Integration
KEYWORDS: Lithography, Calibration, 3D modeling, Scanning electron microscopy, Printing, Design for manufacturing, Semiconducting wafers, Prototyping, Process modeling, Resolution enhancement technologies
With the upcoming technology generations, it will become more and more challenging to provide a good yield and a
fast yield ramp. The contribution of Resolution Enhancement Technologies (RET) to Design for Manufacturability
(DfM) targets is to provide a good printability over the whole process window and the control by print image simulation
(PW-ORC) and to identify and remove yield issues imprinted in the drawn layout in early phases of the design flow.
Such a lithography-aware design data flow, which we call LfD (Litho-friendly Design) will be a very important step
towards a fully developed DfM environment.
We report in this paper the application of a LfD design flow used for library cells at the MAPLE, an Infineon 65 nm
design prototype fabricated by Chartered. The results of the process variability analysis are verified by experimental
results (dose-focus exposure matrices).
We perform 3D lithography simulations by using a finite-element
To proof applicability to real 3D problems we investigate
DUV light propagation through a structure of size 9μm x 4μm x 65nm.
On this relatively large computational domain we
perform rigorous computations (No Hopkins) taking into account
a grid of 11 x 21 source points with two polarization directions
We obtain well converged results with an accuracy of the
diffraction orders of about 1%.
The results compare well to experimental aerial imaging results.
We further investigate the convergence of 3D solutions towards
quasi-exact results obtained with different methods.
During the last years, various DfM (Design for Manufacturability) concepts have been proposed and discussed.
Resolution enhancement technologies with the goal to provide reasonable printability over the whole lithographic
process window, and the optimization of these tools and processes by print image simulation (PW-ORC) have become
crucial aspects of DfM today. In addition, designers and layouters will become increasingly involved in yield
discussions, as they will get tools and methods to identify and remove yield issues in the drawn layout. Such a
lithography-aware design data flow, which is called LfD (Litho-friendly Design), is a very important step towards a fully
developed DFM environment.
Recently, the leading EDA tool vendors have provided tools for efficient process window analysis and a scoring of
lithography issues in a form, which is close to productive usability. We report in this paper the implementation of LfD
into the design flow of library cells for the 90 nm and the 65 nm design rule technologies. Specific aspects of such a LfD
flow, like the availability of robust process models in early development stages are discussed as well as appropriate
means to assess the results.
The role the Optical Rule Check (ORC) in the design flow and future directions are discussed, the benefit of the model-based
methodology is illustrated by using realistic layout situations. Concepts for implementation of Litho-friendly
Design (LfD), i.e., of layout optimization and lithography simulations in the pre-tapeout design flow are developed.
We have investigated the dispersion properties of photonic crystal waveguide resonators. A passive InGaAsP/InP slab waveguide structure was used for the fabrication of the samples. The PhC waveguide resonators were defined by the omission of several rows of holes along the ΓΚ or ΓΜ direction of a triangular photonic crystal lattice. In addition, mirrors with a thickness of 1 to 4 rows of holes were inserted into the waveguide. An optimized dry etch process was used to etch the patterns to a depth of 3.5 µm through the waveguide layer. The group delay of the PhC devices was measured using the phase shift technique. The signal of a tunable laser was modulated at 3 GHz using a LiNbO3 Mach-Zehnder modulator and detected with a high-frequency lightwave receiver. A phase sensitive detection with a network analyer measured the phase shift of the transmitted signal, which is proportional to the group delay. Close to the center of the resonances, the chromatic dispersion reaches values of -250 ps/nm and 250 ps/nm. This corresponds to the chromatic dispersion of 15 km standard fiber.
An extremely fast time-harmonic finite element solver developed for the transmission analysis of photonic crystals was applied to mask simulation problems. The applicability was proven by examining a set of typical problems and by a benchmarking against two established methods (FDTD and a differential method) and an analytical example. The new finite element approach was up to 100 times faster than the competing approaches for moderate target accuracies, and it was the only method which allowed to reach high target accuracies.
We report on low-loss light propagation at the communication wavelength of 1.55 µm through straight two-dimensional photonic crystal waveguides patterned into InGaAsP/InP heterostructures. The linear defect waveguides along the ΓK direction of a triangular lattice of air holes were etched deeply into the semiconductor by Cl2/Ar electron cyclotron resonance reactive ion etching. Efficient waveguiding was observed for both polarization directions, although a photonic band gap exists for only one of the polarization states. Propagation losses, determined by the Fabry-Perot resonance method, are as low as 0.2 dB/mm and 1.5 dB/mm for waveguides based on seven and three missing rows of holes, respectively. Waveguide resonators with 100 GHz channel spacing and quality factors up to 15,000 have been realized by inserting photonic crystal mirrors into the waveguides. The dispersion of the resonators was measured using a phase shift technique. Values for the group velocity dispersion range from -250 ps/nm to +250 ps/nm at wavelengths around 1.55 μm, which is sufficient to compensate for the dispersion of 15 km standard single-mode fiber. Controlling the device temperature allows to tune the dispersive properties of the devices.
The "HiPhoCs" program, a cluster of projects supported by the German
Ministry of Education and Research, is focused on the proof of
applicability of planar photonic crystals based on slab waveguides
within telecom transmission lines and optical networks. Results of
the "HiPhoCs" program on modeling and etching aiming at the optimization of device oriented structures in the III-V and SOI material systems are reported as well as their application to key components such as PhC-based WDM-filters, dispersion compensators,
integrated lasers and their coupling to the optical fiber infrastructure.
Two examples of integrating active and passive photonic crystal devices are discussed. A first example integrates two tunable laser diodes with a passive photonic crystal Y-coupler structure. The tunable laser diode is defined by two photonic crystal channel waveguides that are coupled longitudinally through photonic crystal coupling sections. The waveguides have slightly different lengths and hence exhibit slightly different longitudinal mode spacings. The front and rear reflectors are realized by photonic crystal mirrors with lattice dimensions chosen to achieve the desirable mirror reflectivities. Secondly, a passive superprism structure is discussed that can be integrated with an array of photo diodes to build highly integrated receivers for optical networks.
Long-haul point-to-point transmission systems based on wavelength division multiplex (WDM) are worldwide being installed today. Optical networks containing optical ADD/DROP multiplexers (OADMs) and optical cross-connects (OXCs) are currently tested within field trials in order to assess the hardware, operational and installation aspects and requirements. Within the ACTS project ’’PHOTON”, a WDM cross-connected network called ’’PHOTONET” with ? 520km transmission length and an optical cross-connect is realized and operated with 2.5 GBit/s and 10 GBit/s transmission. The presentation gives an overview of the project, focuses on the field trial and the applications.
Some highlights of the development of DWDM systems and components at Siemens are presented. This includes integrated optical DWDM filters in the SiO2/Si and InGaAsP/InP material systems realized as concave reflection gratings on the basis of Rowland and flat-field mountings and as optical phased arrays. An overview of the activities wavelength-switched optical networks with optical ADD/DROP multiplexers and cross connects is given.
This short tour through computer-aided engineering (CAE) for integrated optics reports on the following topics from a CAE point of view: eigenmode analysis beam propagation, coupled mode theories, computer-aided design and some software aspects. Status and trends are discussed in terms of the fully developed CAE scenario of microelectronics. BPM benchmark results are presented to provide a feeling for the predictive power of today's solvers.
Key results of a benchmark test, initiated in 1992 by the Working Group 2 of COST Project 240 at a modelling workshop in Teupitz, Germany, are presented. A great number of algorithms--FFT-BPM, various types of FD-BPM, wide angle approximations, adaptive FE- BPM and MoL-BPM--are compared. The quasi-analytic character of the benchmark tests provides a deeper insight into the absolute accuracy of algorithms.