Two methods to build submicronic self-aligned devices based on SOI MOS technology have been studied. The foreseen application of these techniques is the fabrication of self-aligned double gate SOI MOS transistors. Both of these methods make use of the implantation of a buried mask underneath the active silicon layer and aligned with the top gate. The mask is revealed by a selective etching between doped and undoped polysilicon. In one case Tetra-methyl Ammonium hydroxide solution (TMAH) is used to create a negative mask, etching the undoped zones. In the second case, a positive mask is revealed in a solution made of Hydrofluoric acid, Nitric acid and Acetic acid (HNA), etching the doped zones. Once the mask is revealed, the process differs from a normal CMOS process by the addition of two Chemical Mechanical Polishing (CMP) and bonding steps. The realized demonstrator proves the feasibility of both the positive and negative buried mask.
The effects of various deposition and annealing conditions of Plasma Enhanced Chemical Vapour Deposited (PECVD) oxide films on residual stress, optical index, BHF etch rate, surface roughness for thick PECVD oxide films are investigated. Rapid Thermal Annealing (RTA) and annealing in regular furnaces are both considered and compared. AFM measurements were required to measure the oxide surface roughness. Thick PECVD oxide films of 1.5 μm were deposited on 380 μm bulk silicon wafer. Starting from a conventional recipe the power, the [N2O/SiH4] ratio and the total gas flow were successively varied. An increase of the total gas flow or/and a decrease of power lead to an increase of the BHF etch rate and surface roughness but on the other hand decrease the residual stress. A high ratio N2O/SiH4 yields to oxide with low BHF etch rate but characterized by higher residual stress. RTA reduces the stress and the BHF etch rate drastically and it is more efficient than conventional annealing in standard furnace. Actually, RTA reduces stress in a very short period of time (few seconds) compared to standard annealing, and then it does not contribute to doping diffusion of the already implanted regions of the wafer. From a compressive stress of about 80 MPa, RTA of 15 s leads to a residual stress of only 30 MPa and bring the BHF etch rate to acceptable values in the range of 2000 Α/min for high N2O/SiH4 ratio oxide. One main application of this RTA stress release of oxide is to provide processed wafers with a bow compatible(less than 10 μm) with Chemical Mechanical Polishing (CMP) or wafer bonding.
Boron highly doped silicon is now widely used as etch stop layer in MicroElectroMechanical Systems (MEMS) devices fabrication. The present paper shows the advantages of replacing the p++ Si etch stop layer by a p++ polysilicon layer. The etch rate of Tetramethylammoniunhydroxide (TMAH) is measured for LPCVD polysilicon and silicon doped with Boron at concentrations from 8.1018 up to 4.1020 atoms/cm3 which is the Boron solubility limit into Si. TMAH etch being often used during back-end process, selectivity to aluminium is usually needed. The etch selectivity of various TMAH solutions for p++ Si, p++ Poly and aluminium have been measured, from 25 % to 5 % TMAH pure and mixed with silicon powder and ammonium persulfate. Contrarily to silicon, polysilicon is etched isotropically in TMAH solution which constitutes a great advantage when cavities with vertical walls have to be opened. Although the polysilicon etch rate is higher than the silicon one, the selectivity (doped/undoped) is the same for the both materials, allowing identical uses. Another great advantage of polysilicon is that it can be deposited at any process step and does not require clever epitaxy steps or wafer bonding as for silicon. The surface roughness of the etched Poly region is considerably decreased with TMAH mixed with silicon powder and ammonium persulfate mixture compared to pure 25 % TMAH solution. The definition of buried masks in polysilicon layer through Boron implant is the main foreseen application. The p++ Poly buried mask brings solutions for the fabrication of self-aligned double gate MOS, microfluidic or optical networks in MEMS field.