The miniaturization of the devices into nanoscale has enabled ultra high density chips, but at the cost of increased defect density. In this manuscript, Markov Random Field (MRF) approach is used to evaluate the device reliability in the
presence of high defect density. Both hard and soft errors have been considered. We have presented a NANOLAB based fault model of 8-bit full adder, basic building block being 2:1 multiplexer. At each level, a Triple Modular Redundancy (TMR) is employed to enhance reliability. The results are compared with another 8-bit full adder, designed using logic gates. Assuming defect rate up to 10%, the circuits are evaluated for stuck at faults. Further, we have augmented the NANOLAB tool to include a design library of various types of flip flops. A 4-bit SISO right shift register is used as vehicle for exemplifying our approach. The fault tolerant approach N-Modular Redundancy (NMR) is compared at different levels of granularity and for varying levels of N. It is observed that NMR fails to provide the device fault tolerance when defect rate is higher than a threshold value.