There are different approaches for alignment sampling optimization. In order to determine, which approach is optimal, OPAL run-to-run simulations<sup>1</sup> must be executed using the result of the different sampling optimization. This means that there is a two-step approach: first, an iterative sampling optimization algorithm that results in optimal overlay modeling. Then, a run-to-run simulation is done to verify the impact on the overlay performance.<p> </p> In this study, we investigate on the behavior of four different approaches to alignment sampling optimization on four different layers and analyze which approach is most suitable for which layer.
It was proven that higher order intra-field alignment data modeling and correction has the potential to improve overlay performance by correcting reticle heating and lens heating effects intra-wafer and wafer- to-wafer.<sup>1 </sup>But there were also challenges shown that needed further investigation. As the alignment measurement is done on a coordinate system with absolute positions, the modeled iHOPC values might be high. A suitable method needs to be developed to distinguish between tool-to-tool offsets, process influence and layer-to-layer tool stack effect. In this paper we will take the next step and evaluate the overlay improvement potential by using intra-field alignment data in an overlay feed-forward simulation. An overlay run-to-run simulation is afterwards performed to estimate the optimization potential. To simulate higher order intra-field overlay, dense alignment data is needed. Facing the challenge of optimizing the number of measured marks but not losing relevant information, an intra-field alignment mark sampling optimization is done to find the best compromise between throughput and overlay accuracy.
In leading edge lithography, overlay is usually controlled by feedback based on measurements on overlay targets, which are located between the dies. These measurements are done directly after developing the wafer. However, it is well-known that the measurement on the overlay marks does not always represent the actual device overlay correctly. This can be due to different factors, including mask writing errors, target-to-device differences and non-litho processing effects, for instance by the etch process.<sup>1</sup> <p> </p>In order to verify these differences, overlay measurements are regularly done after the final etch process. These post-etch overlay measurements can be performed by using the same overlay targets used in post-litho overlay measurement or other targets. Alternatively, they can be in-device measurements using electron beam measurement tools (for instance CD-SEM). The difference is calculated between the standard post-litho measurement and the post-etch measurement. The calculation result is known as litho-etch overlay bias. <p> </p>This study focuses on the feasibility of post-etch overlay measurement run-to-run (R2R) feedback instead of post-lithography R2R feedback correction. It is known that the post-litho processes have strong non-linear influences on the in-device overlay signature and, hence, on the final overlay budget. A post-etch based R2R correction is able to mitigate such influences.<sup>2</sup><p> </p> This paper addresses several questions and challenges related to post-etch overlay measurement with respect to R2R feedback control. The behavior of the overlay targets in the scribe-line is compared to the overlay behavior of device structures. The influence of different measurement methodologies (optical image-based overlay vs. electron microscope overlay measurement) was evaluated. Scribe-line standard overlay targets will be measured with electron microscope measurement. In addition, the influence of the intra-field location of the targets on device-to-target shifts was evaluated.
Before each wafer exposure, the photo lithography scanner’s alignment system measures alignment marks to correct for placement errors and wafer deformation. To minimize throughput impact, the number of alignment measurements is limited. Usually, the wafer alignment does not correct for intrafield effects. However, after calibration of lens and reticle heating, residual heating effects remain. A set of wafers is exposed with special reticles containing many alignment marks, enabling intra-field alignment. Reticles with a dense alignment layout have been used, with different defined intra-field bias. In addition, overlay simulations are performed with dedicated higher order intra-field overlay models to compensate for wafer-to-wafer and across-wafer heating.
Advanced processing methods like multiple patterning necessitate improved intra-layer uniformity and balancing monitoring for overlay and CD. To achieve those requirements without major throughout impact, a new advanced mark for measurement is introduced. Based on an optical measurement, this mark delivers CD and overlay results for a specified layer at once. During the conducted experiments at front-end-of-line (FEOL) process area, a mark selection is done and the measurement capability of this mark design is verified. Gathered results are used to determine lithography to etch biases and intra-wafer signatures for CD and overlay. Furthermore, possible use cases like dose correction recipe creation and process signature monitoring were discussed.
Although the Numerical Aperture (NA) has been greatly improved from 0.93 (dry) to 1.35 (wet) by the introduction of
modern water immersion 193nm scanner since 2001, the realistic single exposure photolithography printing for mass
production is still limited to ~40nm, even with the help of a variety of Resolution Enhancement Techniques (RETs).
Theoretically, the 193nm immersion scanner with high index fluid or Extreme UV (EUV) scanner with a significantly
shorter wavelength of 13.5nm would be the logical successors to water immersion 193nm scanner. However, considering
tremendous technical difficulties to work with high index fluids and relatively immature and very low productivity of
EUV at the moment, it's likely that both candidates have little chance to entering production prior to 2012. Additionally,
the production schedule can be further pushed out due to formidable initial investment for the costly equipment and
consumables associated with EUV given the present worldwide economic recession. Nano-imprint may be attractive for
its low cost and versatile nature, however, long-term stability and logistics under production stress yet to be established.
The hope to continue the thrust of Moore's Law into the sub-40nm regime before EUV era heavily counts on the success
of the so-called Double Patterning Techniques (DPT).
A variety of integration schemes have been developed or are still under development to harness the full capacity of DPT.
Among them the spacer double patterning approach stands out because of the self-aligned characteristics and a
cumulative great deal of experience on the handling of the spacer-related processes in traditional CMOS process
integration. The final goal of most research works around Self-Aligned Double Patterning (SADP) focuses on achieving
minimal added cost and high quality printing at the same time. However, most of the time the quality and the cost are
compromised by applying non-production proven new material/new hardware and/or fancy integration approaches. In
our study we purposely apply a more "classical" and relatively conservative integration scheme, with all unit process
steps long proven in previous volume production. By carefully optimizing the relative CMP, films deposition, etch and
cleaning processes, we are able to demonstrate 30nm line/space patterns by an NA 0.93 dry 193nm scanner with optimal
CDU better than 3nm and high frequency line edge roughness (LER) close to 2nm/side. Additionally, by analyzing
wafer quality for alignment and alignment residual in various alignment & overlay mark designs, projected residual
overlay as little as 4nm can be readily obtained.
In order to reduce the overall size of device features, continuing development in the low k1 lithography process is essential for achieving the feature reduction. Although ArF immersion lithography has extended the feature size scaling to 45nm node, investigation of low k1 lithography process is still important for either ArF dry or wet lithography. Double patterning is one procedure pushing down the k1 limit below 0.25. It combines the multilayer hard mask application and resist shrinkage process to get the feature size reduced to quarter pitch of the illumination limit. In recent spin-on hard mask studies, silicon containing bottom antireflective coatings (BARC) have been developed to combine the function of reflective control and great etching selectivity to the photoresist. Trilayer resist including the photoresist, silicon containing BARC and planarizing organic underlay can improve the reflectivity by optical index tuning of dual hard mask layer effectively and reduce photoresist thickness to avoid the pattern collapse with small features. In our study, we found some interesting characteristics of trilayer resist could be used for double patterning technology and made the low k1 process more feasible. This procedure we investigated can make the feature size of half pitch reduce to 37nm and beyond at 0.92NA under ArF dry lithography. Among the resolution enhancement for ArF dry illumination, double patterning scheme, overlay controllability and pattern transfer process by reactive ion etching (RIE) will be discussed in this paper.
Small contact hole patterning had become the most difficult task in optical lithography as design rule of semiconductor
continuously shrinks below 65nm. Conventional contact hole scheme need to avoid side-lobe and conduct complicated
dense-isolated bias for resolution enhancement and depth of focus (DOF) improvement. To overcome this issue, some
RETs (Resolution Enhancement Techniques) by process had been investigated, like RELACS (resolution enhancement
lithography assisted by chemical shrink). RELACS is one of feasible procedures which could provide enough
improvement in resolution, photo-resist profile, DOF, and CD uniformity (CDU). Proximity effect is one of significant
topics to evaluate chemical shrink bias of different type contacts. Research of shrink bias of different size and pitch
contacts had been investigated broadly in the past. In general, the constant bias of shrinkage for difference pattern sizes
was an assumption. However, according to our evaluative results, we had characterized the correlation about the shrink
bias versus pattern size. In this paper, we not only show DOF, CDU, shrink bias of RELACS, but also present chemical
shrink bias of different size and different pitch contact holes and then we could follow this correlation rule to define
general rule for proximity effect correction.