Mr. Richard J. Dare Profile

Richard J. Dare

Engineer at Broadcom Inc

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Proceedings Article | 12 May 2005 Paper

Feature profile control and the influence of scan artifacts

Richard Dare, Paul Rowland, Terrence Zavecz

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.600225

KEYWORDS: Reticles, Semiconducting wafers, Scanners, Metrology, Systems modeling, Scanning electron microscopy, Critical dimension metrology, Scatterometry, Data modeling, Contamination

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Competitive high volume semiconductor manufacturing yields require that critical feature profiles be continually monitored for uniformity and production control. Historically this has involved long and tedious analyses of Scanning Electron Microscope (SEM) photos that resulted in an average feature profile or a qualitative comparison of a matrix of black and white images. Many factors influence profiles including wafer flatness, focus and film thicknesses. Characterizing profile uniformity as a function of these parameters not only stabilizes high product yields but also significantly reduces the time spent in problem aversion and solution discovery. Scatterometry uniquely provides the combination of feature metrics and spatial coverage needed to monitor production profiles. The vast amount of data gathered by these systems is not well handled by classic statistical methods. A more practical approach taken by the authors is to apply spatial models to the profile data to determine the relative stability and contributions of film, substrate and the exposure tool to process perturbations. Recent work performed by Agere and TEA Systems is shown to be capable of quantitatively modeling the relative contributions of lens slit, reticle-scan and lens degradation to feature size and side-wall angle (SWA). This work describes the models used and the slit-and-scan contributions that are unique for each exposure tool. Finally it is shown that the direction and linearity of the reticle scan can be a contributing factor to the feature profile error budget with direct influence production image stability.

Proceedings Article | 24 May 2004 Paper

Logic gate scanner focus control in high-volume manufacturing using scatterometry

Richard Dare, Bryan Swain, Michael Laughery

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.533835

KEYWORDS: Scanners, Process control, Lithography, Semiconducting wafers, Control systems, Photoresist materials, Scatterometry, Logic devices, Scanning electron microscopy, Photoresist processing

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Tool matching and optimal process control are critical requirements for success in semiconductor manufacturing. It is imperative that a tool’s operating conditions are understood and controlled in order to create a process that is repeatable and produces devices within specifications. Likewise, it is important where possible to match multiple systems using some methodology, so that regardless of which tool is used the process remains in control. Agere Systems is currently using Timbre Technologies’ Optical Digital Profilometry (ODP) scatterometry for controlling Nikon scanner focus at the most critical lithography layer; logic gate. By adjusting focus settings and verifying the resultant changes in resist profile shape using ODP, it becomes possible to actively control scanner focus to achieve a desired resist profile. Since many critical lithography processes are designed to produce slightly re-entrant resist profiles, this type of focus control is not possible via Critical Dimension Scanning Electron Microscopy (CDSEM) where reentrant profiles cannot be accurately determined. Additionally, the high throughput and non-destructive nature of this measurement technique saves both cycle time and wafer costs compared to cross-section SEM. By implementing an ODP daily process check and after any maintenance on a scanner, Agere successfully enabled focus drift control, i.e. making necessary focus or equipment changes in order to maintain a desired resist profile.

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