Line-end pullback has been an issue for photoresist patterning for many years. The two-dimensional nature of line-ends leads to increased deprotection of the resist and shortening of the resist features. From a lithographic standpoint, line-end pullback can be mitigated to some extent using optical proximity correction (OPC). However, as the space between line-ends gets smaller, a trade-off exists with respect to OPC. Over-correction of the line-end on the reticle by the addition of hammerheads can lead to bridging. In some cases, the line-end spacing can actually be less than design rules. The poor aerial image contrast at these line-ends can lead to sloped profiles as well as pullback. The line-end slope depends on the resist contrast, the OPC, and the target line end-to-end space. These sloped line ends lead to increased pullback during the subsequent gate etch process. For gate patterning, a resist trim step is often utilized prior to etching a hardmask and polysilicon. During each etch step the resist line-end is quickly eroded due to the sloped profile. In this paper, we present a novel post-develop processing technique for improving the line-end profile of patterned photoresist. This improvement in the line-end profile results in less pullback during subsequent etch processing. After development, a patterned photoresist film is treated to a gas phase fluorination process. The fluorination process leads to substitution of F for H in the polymer matrix of the resist film, and causes the resist to swell. This swelling causes the line-end profile to become more vertical due to the fact that the base of resist features are anchored to the substrate, and only the top portion of the resist features will swell. This improvement in the line-end profile is shown to reduce line end-to-end spacing by 20-30% after etch. Cross-sectional images show the improvement throughout the partitioned etch process. Simulation results verify that a more vertical line-end slope is sufficient to decrease line-end pullback during etch.
As semiconductor gate lengths shrink, photoresist trends toward thinner films. Thick photoresist films are not desirable because they tend to absorb more light, require higher energies to pattern, increase pattern collapse, and subtract from depth of focus and exposure latitude. The minimum thickness of implant photoresist is governed by the stopping power of the photoresist for the ion type and the energy of the implant. Relatively high energy implants and/or lower ion stopping power in the photoresist require thicker photoresist films. These problems can be mitigated through a novel photoresist fluorination process. The fluorination process results in the replacement of H atoms by heavier F atoms effectively increasing the molecular weight of the fluorinated film and its ability to block ion implantation. This straightforward and cost-effective process is investigated for use with a standard 248 nm dyed photoresist. Substrate damage probe measurements and Secondary Ion Mass Spectrometry depth profiles show species-dependent ion implant masking improvements of up to 40 % for fluorinated photoresist versus as-developed photoresist. Geometric and process margin arguments are discussed for thinning photoresist where angled implants are needed or process capability is insufficient. Finally, electrical data is presented that demonstrates the manufacturability of these fluorinated and thinned photoresist films.
The requirements for critical dimension control on gate layer for high performance products are increasingly demanding. Phase shift techniques provide aerial image enhancement, which can translate into improved process window performance and greater critical dimension (CD) control if properly applied. Unfortunately, the application of hard shifter technology to production requires significant effort in layout and optical proximity correction (OPC) application. Chromeless Phase Lithography (CPL) has several advantages over complementary phase mask (c:PSM) such as use of a single mask, and lack of phase placement 'coloring' conflicts and phase imbalance issues. CPL does have implementation issues that must be resolved before it can be used in full-scale production. CPL mask designs can be approached by separating features into three zones based on several parameters, including size relative to the lithographic resolution of the stepper lens, wavelength, and illumination conditions defined. Features are placed into buckets for different treatment zones. Zone 1 features are constructed with 100% transmission phase shifted structures and Zone 3 features are chrome (binary) structures. Features that fall into Zone 2, which are too wide to be defined using the 100% transmission of pure CPL (i.e. have negative mask error factor, MEEF) are the most troublesome and can be approached in several ways.
The authors have investigated the application of zebra structures of various sizes to product type layouts. Previous work to investigate CPL using test structures set the groundwork for the more difficult task of applying CPL rules to actual random logic design layouts, which include many zone transitions. Mask making limitations have been identified that play a role in the zebra sizing that can be applied to Zone 2 features. The elimination of Zone 2 regions was also investigated in an effort to simplify the application of CPL and improve manufacturability of reticle through data enhancements.
Patterning of sub-100nm contacts for sub-90-nm-node devices is one of the primary challenges of photolithography today. The challenge involves achieving the desired resolution while maintaining manufacturable process windows. Increases in numerical aperture and reductions in target CDs will continue to shrink process windows and increase mask error factor resulting in larger CD variation. Several techniques such as RELACS, SAFIER, and resist reflow have been developed to improve the resolution of darkfield patterns such as contacts and trenches. These techniques are all post-develop processes applied to the patterned resist. Reflow is a fast process with low cost of ownership, but has two major disadvantages of high temperature sensitivity and large proximity bias. SAFIER and RELACS both have much slower throughput and higher cost of ownership than reflow. SAFIER also is sensitive to temperature and has large proximity bias. In this paper, a novel process is described that reduces the diameter of contact holes in resist up to 25nm without proximity effects. This process uniformly swells the resist film resulting in a shrink of patterned holes or trenches. Results are shown for 248nm and 193nm single layer resists, and a 193nm bilayer resist. This process has the potential to be high throughput with low cost of ownership similar to reflow techniques but without the proximity effects and thermal sensitivity observed with reflow.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
We have exposed 10 wafers on the Engineering Test Stand (ETS), the 0.1 NA EUV scanner at Sandia National Laboratories in Livermore, CA. The EUV reflective mask was fabricated in-house using a Ta-based absorber stack on Mo/Si multilayers. The printed wafers contained different line sizes and pitches, line-end shortening measurement structures, contact holes, and patterns for estimating absorber defect printability. The depths of focus of each feature are typically 2 um due to the small NA of the scanner, and these should decrease by at least a factor of 6.25 as the NA's increase to 0.25. The data from measurements of line size through pitch and line-end shortening test structures indicate that both 1D and 2D optical proximity correction will be required. Defects that are either notches in or protrusions from absorber lines are the first to print, and they begin to print when they reach approximately 15~nm (1X) in size. This size threshold is in accordance with the 2003 ITRS specifications. We also report the first printing of SRAM bitcells with EUV lithography.
The high absorption of extreme ultraviolet (EUV) radiation by all materials necessitates the use of thin photoresist films with thicknesses less than 200 nm for EUV lithography to ensure good imaging. Thinning the resist thickness below 150 nm or even 100 nm may produce benefits such as increased sensitivity, larger process latitude, and increased resolution. However, these potential benefits as well as the required need for thin resists come at the expense of reduced etch resistance. EUV lithography will require the use of some type of thin imaging technique such as top-surface imaging, bilayer resists, or single layer resists with hardmasks in order to achieve the necessary etch resistance. In this paper, we discuss results that demonstrate the feasibility of using thin resist approaches for fabricating working devices. We have successfully fabricated working 130-nm-node SRAMs using a single layer 248 nm ultrathin resist (< 150-nm-thick) with a hardmask for both gate and contact layers on the same wafer. This result represents the first demonstration of working devices fabricated using ultrathin resists on multiple device layers. We also present initial patterning experiments using a 193 nm bilayer resist for brightfield applications such as the gate layer, and compare imaging performance to that of a 193 nm single layer resist. The advantages and disadvantages of the single layer and bilayer approaches are discussed.
Resist pattern edge roughness is expected to cause degradation of transistor performance as gate lengths shrink below 40 nm. In the literature line edge roughness (LER) has been linked to many optical and chemical variables associated with the lithography process. As resist trim etch becomes more aggressive over time, LER on etched gates becomes less linked to the roughness in resist, and more to a product of the coupled lithography and etch processes. The aspect ratio of trimmed resist features increases and patterns become susceptible to pattern collapse, bending and tearing. Conversely if aspect ratios are maintained through the trim process, then the ability of the resist to protect the substrate from the final etch is degraded as the resist thickness decreases. A novel method of resist fluorination is presented that significantly reduces LER and pattern deformations such as collapse, tearing and bending. Experimental data shows that resist fluorination can make possible sub-30 nm etched polysilicon gates at aspect ratios on the order of 5:1. The same fluorination process yields LER improvements of 15% to 20% on average with largest improvements in the mid-range roughness frequencies of 10 - 50 μm<sup>-1</sup>. The length scale, or inverse of frequency, is also used in the study. The resist fluorination process is described as it is used in the study. Experimental and analytical data show how the process is reduced to practice and how LER and pattern deformation are improved. The fluorination process is simple to integrate into a standard wafer flow, has low cost of ownership, and yields large process improvements.
We have demonstrated the fabrication of working 130 nm-node SRAMs with high yield using single layer ultra-thin resist (UTR) integrations. Transistor gates were fabricated using 140-nm-thick resist films in combination with a single layer, inorganic anti-reflective coating (ARC) that also acted as a hardmask (HM). An aggressive ARC/HM removal process was developed to enable the use of a thick ARC/HM. The thick ARC/HM was necessary to allow the incorporation of a resist trim step prior to polysilicon gate etch that reduced the transistor gate lengths in silicon from the printed critical dimension (CD) in resist. Transistor performance for both NMOS and PMOS devices with UTR-fabricated gates was equivalent to the performance of standard transistors. Working SRAM arrays were fabricated using UTR at the gate layer that achieved natural yield within 10% of the yield achieved with a thick resist process, and in some cases, with yield that exceeded the thick resist process. CD control for the UTR gate photo process was equivalent to the baseline photo process, and the UTR gate photo process was optimized to increase device yield. Contacts fabricated using 120-nm-thick resist films exhibited electrical characteristics equivalent to those fabricated with standard processes, and yielding SRAM devices were fabricated using UTR at the contact layer. Defect inspection of UTR contact patterning detected the formation of pinholes in the UTR films; however, the formation of pinholes was found to be dependent upon substrate-resist interactions.
Fabrication of integrated circuits with sub-100 nm features will require tight control of critical dimensions, line edge roughness, and profiles of patterned features. The drive to smaller features will be accomplished principally by reduction of exposure wavelength in lithography systems. The use of 157 nm and EUV lithography will most likely require thin resists with thicknesses less than 150 nm due to the high absorption of materials at these wavelengths. High NA and low k1 systems for 193 nm lithography may also benefit from the use of thin photoresist processes. The properties and behavior of thin resists are expected to be strongly affected by interfaces, and thus, the lithographic performance of resists with sub-200-nm thickness is of interest. In this paper, we present a study of the lithographic behavior of a single layer 193 nm resist at different thicknesses ranging from 90 nm to 240 nm. The line edge roughness (LER) of 193 nm resist films increased dramatically with decreasing film thickness, but increasing the concentration of photoacid generator (PAG) and base quencher in the films helped reduce the LER. The process latitude for dense 110 nm lines (250 nm pitch) imaged using a single resist formulation with high PAG/quencher concentration was experimentally determined for 4 thicknesses (90 nm to 240 nm) by changing only the spin speed. The process latitude was found to be almost equivalent for sub-200 nm thick films, however, sub-100 nm thick films exhibited much higher LER than the thicker resist films. The performance of the 193 nm resist was compared to a 248 nm resist coated at thicknesses ranging from 104 nm to 260 nm. The 248 nm resist exhibited a decreasing trend in both exposure latitude and depth of focus with decreasing film thickness. Time-of-flight secondary ion mass spectrometry was used to investigate the distribution of PAG in the resist films. Some of the resist behavior of sub-150 nm thick films could be explained due to non-uniform PAG distribution.
The 2001 edition of the International Technology Roadmap for Semiconductors establishes line-edge roughness (LER) requirements for patterned resist lines. Little is known, however, about how LER affects device performance or about how much LER is acceptable for a given technology. Our work seeks to answer these questions by combining process modeling, three-dimensional (3D) device modeling, and experiment to investigate the amount of LER that can be varied by process conditions and the levels to which LER must be controlled. Our process models show the expected trade-offs between resist diffusion, LER, and resolution, and they show that much of the high-frequency, high-amplitude roughness can be reduced through appropriate etch and implant diffusion processes. The low-frequency roughness, on the other hand, is much harder to eliminate. Experimentally, we have found that the aerial image quality and the etch process have the largest effect on the edge roughness transferred to polysilicon lines, and the roughness after etch is distributed over a broad range of frequencies. The 3D device models indicate that the amount of roughness that gets transferred to the junctions will dominate the electrical behavior, and the effects will likely be different for PMOS devices than NMOS devices.
Tight control of very small transistor gate CDs is one of the most difficult problems in advanced device patterning. Line-edge roughness on these small gate lines has become a serious issue with 193nm lithography and is only expected to worsen with 157nm and EUV lithography. Methods are needed that can minimize line-edge roughness while also enabling the patterning of small gate features. We have analyzed the use of a simple and manufacturable post-develop bake step, a 'hardbake', that controllably reduces both gate resist CDs and to line-edge roughness. Hardbake resist shrinkage is a well-known phenomena from earlier Novolak resist processing, but has not been investigated for chemically amplified resists as much as other CD slimming techniques. Our tests have been performed for different chemically amplified 193nm and EUV-type (essentially reformulated 248nm) resists. The results of our experiments show considerable potential for certain types of resists to provide gate CD control benefits from either roughness reduction or CD slimming.
Low-k<SUB>1</SUB> imaging, high-NA optics, pattern collapse, and the absorption of resist materials in 157-nm and EUV lithographies are driving down the thickness of the photoresist layer in integrated circuit fabrication processes. Although devices and test structures have been successfully fabricated with resist films thinner than 160 nm on various levels, the fabrication of working devices with high yield using ultrathin resist (UTR) integrations on multiple device layers has yet to be demonstrated. In the present work, gates have been patterned with 140-nm thick resist films with 10-15 defects per wafer, none of which are specific to the UTR process. Similar UTR gates were also patterned over 80-nm steps with no defects associated with the topography. The UTR NMOS transistors in this work have 10 pA/micrometers leakage and 400 (mu) A/micrometers drive currents, but the PMOS transistors do not perform as well. The line-edge roughness (LER) is 5-8 nm 3(sigma) depending upon exposure mask (binary vs. PSM) and substrate. Etching into 100 nm of crystalline Si reduces the LER to 4-7 nm 3(sigma) . The power spectral densities of the roughness have a Lorentzian shape, and most of the roughness occurs over length scales larger than 100 nm. Contact chains with electrical characteristics comparable to standard processes were fabricated with 120-nm thick resist films. Polysilicon as thick as 150 nm was etched successfully with 80-nm thick resist films and hardmasks.
The lithographic performance of a single layer 193nm resist platform, Sumitomo PAR707, was evaluated for 100nm node patterns for thicknesses ranging from 313nm to 60nm. We first demonstrated that the standard resist formulation could not be used for sub-200nm thicknesses because of unacceptable line edge roughness (LER). We then evaluated the influence of the concentration of photo acid generator (PAG) in the resist formulation of LER over the thickness range of 313nm to 60nm. High PAG loading was found to decrease LER significantly for sub-200nm thicknesses. Using the optimal formulation for minimal LER for a given thickness, process latitudes for 100nm node patterns were determined. The overall dose-focus latitudes were found to remain very close for all thicknesses, with slightly larger latitude for thicker imaging layers.