Earlier [1, 2] work highlighted an integrated process for electrically functional 12 nm half-pitch copper interconnects in an ultralow-k interlayer dielectric (ILD). In this paper, we focus on understanding and reducing undesired effects such as pattern asymmetry/distortion, and line undulation/ collapse. Key defect modes and possible solution paths are discussed. Line undulation can occur when the ILD feature changes shape under the stress of the sacrificial hard mask(s) (HM) during patterning, resulting in “wavy” instead of straight features. The amount of undulation is directly related to mechanical properties such as elastic modulus, residual stresses of patterned HMs and the ILD, as well as the dimensions and aspect ratio of the features. Line collapse is observed post wet-clean processing when one or more of the following is true - Insufficient ILD mechanical strength, excessive pattern aspect ratio, or non-uniform drying. Pattern asymmetry, or unequal critical dimensions (CD) of trenches defined by the same backbone, is a typical problem encountered during spacer-based pitch division. In pitch quartering (P/4), three different trench widths result from small variations in backbone lithography, spacer CD and etch bias. Symmetric patterning can be achieved through rigorous control of patterning processes like backbone definition, spacer deposition and downstream etches. Plasma-based ash and energetic metal deposition were also observed to degrade patterning fidelity of ultra low-k film, and also need to be closely managed.
Intel has reported on three separate styles and applications of strong phase shift masks (PSMs) over the last decade
including alt-PSM for gate patterning, alt-PSM with assist features for contact patterning and Pixelated Phase Masks
(PPMs) for metal layer patterning. Each had a prominent role in Intel's Design For Manufacturing (DFM) infrastructure development in terms of design rules and DFM tooling. By gradually inserting design rule changes for alt-PSM for gate patterning starting from the 130nm technology node, density and design impact were minimally effected.
Alt-PSM for contact layer required development of complex methods of SRAF placement and coloring while also
forcing advances in phase shift mask manufacturing infrastructure. Pixelated phase masks for metal patterning when
combined with Inverse Lithography Techniques (ILTs) were successful in supporting a high level of flexibility for metal
design rules including multiple feature sizes, pitches and two-dimension content.
Pixelated phase masks rendered from computational lithography techniques demand one generation-ahead mask
technology development. In this paper, we reveal the accomplishment of fabricating Cr-less, full field, defect-free
pixilated phase masks, including integration of tapeout, front-end patterning and backend defect inspection, repair,
disposition and clean. This work was part of a comprehensive program within Intel which demonstrated microprocessor
To pattern mask pixels with lateral sizes <100nm and vertical depth of 170nm, tapeout data management, ebeam write
time management, aggressive pattern resolution scaling, etch improvement, new tool insertion and process integration
were co-optimized to ensure good linearity of lateral, vertical dimensions and sidewall angle of glass pixels of arbitrary
pixelated layout, including singlets, doublets, triplets, touch-corners and larger scale features of structural tones
including pit/trench and pillar/mesa. The final residual systematic mask patterning imperfections were corrected and
integrated upstream in the optical model and design layout.
The volume of 100nm phase pixels on a full field reticle is on the order tera-scale magnitude. Multiple breakthroughs in
backend mask technology were required to achieve a defect free full field mask. Specifically, integration of aerial
image-based defect inspection, 3D optical model-based high resolution ebeam repair and disposition were introduced.
Significant reduction of pixel mask specific defect modes, such as electro static discharge and glass pattern collapse,
were executed to drive defect level down to single digit before attempt of repair. The defect printability and repair yield
were verified downstream through silicon wafer print test to validate defect free mask performance.
This work describes the advantages, tolerances and integration issues of using Pixelated Phase Masks for patterning
logic interconnect layers. Pixelated Phase Masks (PPMs) can act as variable high-transmission attenuated phase shift
masks where the pixelated phase configuration simultaneously optimizes OPC and SRAF generation. Thick mask
effects help enable PPMs by allowing larger minimum pixel sizes and phase designs with near equal sized zero and piphase
regions. PPMs with a 3-tone pixel mask (un-etched glass, etched glass, chrome) offer more flexible patterning
capability compared to 2-tone pixel mask (no chrome) style but at the detriment of a more complex mask making
process. We describe the issues and opportunities associated with using PPMs for patterning a 65nm generation first
level metal layer of a micro-processor.
Novel RET-Pixelated Phase Mask (PPM) is proposed as a novel Resolution Enhancement Technique (RET). PPM is
made of pixels of various phases with lateral dimensions significantly smaller than the illuminating radiation
wavelength. Such PPM with a singular choice of pixel dimensions acts as a mask with variable phase and transmission
due to radiation scattering and attenuation on pixel features with the effective intensity and phase modulated by the
pixel layout. Key properties of the pixelated phase masks, the steps for their practical realization, and the benefits to
random logic products discussed. Wafer patterning performance and comparative functional yield results obtained for a
65nm node microprocessor patterned with PPM, as well as current PPM limitations are also presented.
For tight pitch patterning with sub-wavelength mask features, simulations and wafer data show that many mask stacks
that provide superior image contrast, can provide inferior MEEF performance. For example, 6% MoSi EPSM is found
to have higher MEEF than binary masks despite having better contrast and exposure latitude when equal lines and spaces
on the mask are used to pattern equal lines and spaces on the wafer. Likewise, the deposition of SiO2 on-top of the
chrome surface of a binary mask improves contrast but degrades MEEF compared to a binary mask. When contrast is
varied by mask stack or by print bias, MEEF is poorly correlated with contrast and often increases with increasing
contrast. The optimal print bias for exposure latitude is significantly different than the optimum print bias for MEEF.
MEEF, on the other hand, is highly correlated with the difference between maximum and minimum intensity when one
varies mask stack, print bias and illumination. Analytical MEEF equations are derived that support this strong
relationship between MEEF and the difference between maximum and minimum intensity.
The use of alternating phase shift masks (Alt-PSMs) for poly gate patterning is becoming a well-established method for reducing gate critical dimension (CD) and variability. The application of alt-PSM for other device layers and for improving resolution (minimum pitch) is less developed due to more complex layouts, more stringent mask constraints and cost of ownership restrictions. Resolution of contact pairs and nested contacts is found to be improved using alt-PSM compared to embedded PSMs (EPSMs). To improve the process window of semi-nested and isolated contacts, sub-resolution phase-shifted assist features are employed on the mask. Square assist features, rather than rectangular assist features, are used to reduce mask fabrication requirements as one can use a larger minimum assist feature dimension. Because of high mask error enhancement factors (MEEFs), assist features with dimensions as large as 75% of the nominal contact size can be used without patterning on the wafer. Compared to using alt-PSM for poly gate patterning the use of alt-PSM for tight pitch patterning places additional constraints on mask manufacturing. The smaller phase regions intrinsic to tight pitch patterning result in tighter phase uniformity and mask defect requirements.
Intel will start high volume manufacturing (HVM) of the 65nm node in 2005. Microprocessor density and performance trends will continue to follow Moore's law and cost-effective patterning solutions capable of supporting it have to be found, demonstrated and developed during 2002-2004. Given the uncertainty regarding the readiness and respective capabilities of 157nm and 193nm lithography to support 65nm technology requirements, Intel is developing both lithographic options and corresponding infrastructure with the intent to use both options in manufacturing. Development and use of dual lithographic options for a given technology node in manufacturing is not a new paradigm for Intel: whenever introduction of a new exposure wavelength presented excessive risk to the manufacturing schedule, Intel developed parallel patterning approaches in time for the manufacturing ramp. Both I-line and 248nm patterning solutions were developed and successfully used in manufacturing of the 350nm node at Intel. Similarly, 248nm and 193nm patterning solutions were fully developed for 130nm node high volume manufacturing.
Inspection and repair of defects represent some of the challenges for the fabrication of 'defect-free' alternating phase-shift masks needed for performance improvements in patterning the polysilicon gate layer of integrated circuit devices. Inspection, metrology, repair, and printability of defects on dark-field alternating phase-shift masks used in dual exposure processes for polysilicon gate layer patterning are discussed in this study. The impact of phase and chrome defects on photoresist features printed at an exposure wavelength of 248 nm is evaluated and compared to the defect signals measured on a mask inspection tool operating at 364 nm. Experimental data on printability and inspection of programmed glass defects with several different phase errors as well as programmed chrome defects are compared to simulations. The effects of the exposure tool focus conditions on phase defect printability are discussed in detail. Phase defect contrast enhancement mechanisms that may enable improvements in phase defect detection during mask inspection using conventional inspection tools are also addressed. Finally, successful repairs of real glass bump defects are demonstrated.
While the use of phase shift masks can improve CD control and allow the patterning of smaller poly gate features, it also introduces new error terms for overlay. Four error terms are discussed: increased sensitivity of image placement to coma-type aberrations, image placement shifts resulting form phase errors, image placement shifts resulting from intensity imbalance between zero and 180 degrees shifter regions, and phase shift mask to trim mask overlay issues. These overlay issues become increasingly important for lower k1 patterning. Likewise, phase defect printability is magnified for lower k1 patterning, increasing the requirements for phase shift mask inspection and repair.
The concept of the iso-aberration dose is introduced and defined as the dose where the 'depth of aberration' is at a maximum. By allowing patterning of small isolated lines closer to the iso-aberration dose, the use of phase shift masks (PSMs) improves critical dimension (CD) sensitivity to lithographic tool aberrations. The use of specialized photo- resist and mask assist feature is also found to improve isolated line CD sensitivity to aberrations. The improvement in aberration sensitivity from PSM results in improved across field linewidth control for some lithographic system but causes degraded CD control for other tools which are optimized for operation with standard binary reticles. Simulations show that the trim mask PSM approach has superior aberration sensitivity for patterning 100nm than multi-phase PSM approaches when the allowed phasewidth is restricted to a maximum value.
Single, multi-phase, and dual, 'hidden-shifter,' phase shift masks are compared via simulation and experiment in terms of line-end patterning fidelity and printability of phase defects. Four phase mask line-ends bend through focus while 'hidden-shifter' line-ends show acceptable performance. For a given phase difference, phase defects are found to be more severe than phase errors in terms of resist CD variations. Phase defect printability is highest at positive defocus. For a typical process window, 60 degree phase defects as small as 100 nm may cause unacceptable CD variations.
Different 1995 - 1996 grade experimental fused silica samples were evaluated for their resistance to UV-induced compaction at 193 nm under elevated sample temperature conditions. Stress induced birefringence was used as a sensitive compaction monitor. We found that compaction rate decreases with increasing sample temperature. Isochronal annealing experiments were performed on two different sets of pre-damaged fused silica samples. Annealing of compaction was observed at temperatures as low as 200 degree(s)C, and an activation energy of 0.1 eV was found.
Using birefringence monitoring, several experimental fused silicas are tested for 193-nm compaction durability. f N ( I J2 't 10.1 All samples exhibit densification that can be described by the equation: (Lip/p )u = 1C · l--7 · - · _.!!_J where 10 10 't 'tis the pulse length ('t0 = lns), Np is the pulse count, K is a constant, and I is the 193-nm energy density (I., = 1 mJ/cm2). The extracted value of K varies from 84ppB to 660ppB for experimental (1995-1996) fused silicas, as much as a factor of two improvement compared to (1990-1994) grades. The role of irradiation geometry in compaction is also investigated using finite element simulations. The net optical path difference formed for a given level of damage is found to increase by approximately 25% when the damage radii is increased from 30% to 70% of the total sample diameter in a relatively thin optical element. Keywords: damage, fused silica, two-photon, densification, compaction, lithography, 193-nm, stress-birefringence
Several experiments are reported to better predict the 193-nm radiation-induced compaction rates of fused silica at lithographic intensities. Birefringence monitoring is capable of measuring the compaction-induced birefringence distribution from modest total fluences. For example, 6 hours at 350Hz with a per pulse energy density of only 1.1mJ/cm2 produces a relative compaction of about 38 ppB and corresponding relative refractive index change of 11 ppB which is easily measured. Moreover, this value of compaction is more than would be predicted by extrapolation from past higher fluence experiments. Compaction follows a non- linear dependence on pulse count. Compaction rates drop with continuing irradiation but do not saturate in the 1-10 ppm compaction range. The dependence of compaction on intensity is found to accurately follow an intensity squared rule that is all data over a wide range of pulse energy densities can be plotted via a single curve. Using this result, one can now scale higher energy density tests to predict damage rates of materials at lower fluences. Although compaction rates can vary by a factor of three over all sample types, we find less than 25 percent variation in compaction rate among UV grade samples.
Five different fused silica types were evaluated for their resistance to UV-induced compaction and color center formation at 193-nm. Real-time monitoring of color- center-induced absorption showed three distinct dependencies of transmission on pulse count. The initial rates of color center formation varied by well over a factor of ten between the materials tested while compaction-induced birefringence rates varied by at most a factor of four. Of the likely candidates for lithographic applications, Corning Excimer Grade 7940 fused silica was the least prone to color center formation while Suprasil 311 showed the lowest compaction rates. The rates of compaction-induced birefringence and color-center-induced absorption from 213-nm radiation were found to increase dramatically under elevated sample temperature conditions. Since a two- photon absorption mechanism is believed to be the catalyst for UV damage to fused silica, two-photon absorption coefficients were characterized at elevated temperatures. The two-photon coefficients at 213-nm for all materials measured including crystalline quartz and under all applied conditions were statistically equivalent, leading to the conclusion that the energy dissipation mechanism, in addition to two-photon absorption, is important to UV damage to fused silica.
Accelerated damage experiments were conducted to better predict the lifetime of fused silica optics under Deep-UV lithographic conditions. Real-time monitoring of UV-induced absorption showed that 193-nm radiation produced color centers four to five times faster that 213-nm radiation. Since the two-photon absorption coefficient at 193-nm is also about five times larger than the 213-nm value, a two-photon initiated damage process was supported. Refractive index changes in irradiated samples extrapolated from stress-induced birefringence distributions and a compaction model correlated with the refractive index changes calculated from interferometry measurements. The rates of UV-induced refractive index changes varied by over a factor of two among five different fused silica types, indicating that fused silica chemistry and processing history effect compaction susceptibility. The compaction rates, when extrapolated down to lithographic intensities, predict that the lifetimes of fused silica optical systems may be limited by UV- damage.