Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for mask end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer’s process margin is shrinking at advanced nodes to a point that classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on sub-resolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. To overcome the limitation of 1D metrics, there are numerous on-going industry efforts to better define wafer-predictive metrics through both standard mask metrology and aerial CD methods. Even with these improvements, the industry continues to struggle to define useful correlative metrics that link the mask to final device performance. In part 1 of this work, we utilized advanced mask pattern characterization techniques to extract potential hot spots on the mask and link them, theoretically, to issues with final wafer performance. In this paper, part 2, we complete the work by verifying these techniques at wafer level. The test vehicle (TV) that was used for hot spot detection on the mask in part 1 will be used to expose wafers. The results will be used to verify the mask-level predictions. Finally, wafer performance with predicted and verified mask/wafer condition will be shown as the result of advanced mask characterization. The goal is to maximize mask end user yield through mask-wafer technology harmonization. This harmonization will provide the necessary feedback to determine optimum design, mask specifications, and mask-making conditions for optimal wafer process margin.
As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask
Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and
CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process.
However, the wafer lithographer’s process margin is shrinking at advanced nodes to a point that the classical mask CD
metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at
advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution
assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity.
These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced
characterization methods in order to optimize the mask process to meet the wafer lithographer’s needs. These advanced
characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot
analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled
We present a novel metrology target design framework using the scanner exit pupil wavefront analysis together with Zernike sensitivity analysis (ZSA) based on the Monte-Carlo technique. The proposed method enables the design of robust metrology targets that maximize target process window (PW) while minimizing placement error discrepancies with device features in the presence of spatial and temporal variation of the aberration characteristics of an exposure tool. Knowing the limitations of lithography systems, design constraints, and detailed lithography information including illumination, mask type, etc., we can successfully design an optimal metrology target. We have validated our new metrology target design (MTD) method for one of the challenging DRAM active layer consisting of diagonal line and space patterns illuminated by a rotated extreme dipole source. We find that an optimal MTD target gives the maximized PW and the strong device correlation, resulting in the dramatic improvement of overall overlay performance. The proposed target design framework is completely general and can be used to optimize targets for different lithography conditions. The results from our analysis are both physically sensible and in good agreement with experimental results.
Overlay control is more challenging when DRAM volume production continues to shrink its critical dimention (CD) to 70nm and beyond. Effected by process, the overlay behavior at wafer edge is quite different from wafer center. The big contribution to worse overlay at wafer edge which causes yield loss is misalignment. The analysis in wafer edge suggests that high order uncorrectable overlay residuals are often observed by certain process impact. Therefore, the basic linear model used for alignment correction is not sufficient and it is necessary to introduce an advanced alignment correction model for wafer edge overlay improvement. In this study, we demonstrated the achievement of moderating the poor overlay at wafer edge area by using a high order wafer alignment strategy. The mechanism is to use non-linear correction methods of high order models ( up to 5th order), with support by the function High Order Wafer Alignment (known as HOWA) in scanner. Instead of linear model for the 6 overlay parameters which come from average result, HOWA alignment strategy can do high order fitting through the wafer to get more accurate overlay parameters which represent the local wafer grid distortion better. As a result, the overlay improvement for wafer edge is achieved. Since alignment is a wafer dependent correction, with HOWA the wafer to wafer overlay variation can be improved dynamically as well. In addition, the effects of different mark quantity and sampling distribution from HOWA are also introduced in this paper.
The results of this study indicate that HOWA can reduce uncorrectable overlay residual by 30~40% and improve wafer-to-wafer overlay variation significantly. We conclude that HOWA is a noteworthy strategy for overlay improvement. Moreover, optimized alignment mark numbers and distribution layout are also key factors to make HOWA successful.
The etch loading effect from wafer center to wafer edge results in worse Bit-line Contact layer (CB) to Gate Conductor layer (GC) overlay alignment performance at the wafer edge which directly impacts device yield. One workaround for this is to introduce additional image shifts during exposure at the edge of the wafer however this will reduce throughput due to the extra time required for wafer measurement (additional leveling scans) and extra exposure time (additional image). We demonstrate a new method which can avoid this overhead using Correction Per Exposure (CPE).
We are proposing to use CPE with manually generated overlay corrections. In this way, we are achieving the necessary wafer-edge overlay compensation, and there is no throughput-loss because there is no extra-routing.
It is evident that DRAM ground rule continues to shrink down to 90nm and beyond, overlay
performance has become more and more critical and important. Wafer edge shows different behavior from
center by processes, e.g. a tremendous misalignment at wafer edge makes yield loss . When a conventional
linear model is used for alignment correction, higher uncorrectable overlay residuals mostly happen at
wafer edge. Therefore, it's obviously necessary to introduce an innovational alignment correction methdology to reduce unwanted wafer edge effect. In this study, we demonstrate the achievement of moderating poor overlay in wafer edge area by a novel zone-dependent alignment strategy, the so-called "Zone Alignment (ZA)". The main difference between the conventional linear model and zone alignment strategy is that the latter compensates an improper averaging effect from first modeling through weighting all surrounding marks with a nonlinear model. In addition, the effects of mark quantity and sampling distribution from "Zone Alignment" are also introduced in this paper. The results of this study indicate that ZA can reduce uncorrectable overlay residual and improve wafer-to-wafer variation significantly. Furthermore, obvious yield improvement is verified by ZA strategy. In conclusion, Zone alignment is the noteworthy strategy for overlay improvement. Moreover, suitable alignment map and mark numbers should be taken into consideration carefully when ZA is applied for further technology node.