KEYWORDS: Fin field effect transistors, Line edge roughness, Doping, Optical lithography, Transistors, Computer simulations, Field effect transistors, Line width roughness, CMOS technology, Device simulation
In current CMOS technology, parameter variations are playing a vital role in limiting the benefits of downscaling, especially in the nanodomain. This work presents the investigation of random dopant fluctuation (RDF) in several possible line-edge roughness (LER)-induced fin shapes of spacer- (i.e., correlated LER) and resist- (i.e., uncorrelated LER) defined patterning techniques for a 14-nm FinFET structure. The three-dimensional (3-D) technology computer-aided design simulation on a large statistical ensemble has been carried out to analyze the impact of the RDF on various device parameters such as threshold voltage, drive current, off current, and drain-induced barrier lowering. It is observed that the impact of RDF on electrical parameters mainly depends on the fin shape and is dominant in all resist-defined FinFET structures. It is also found that the impact of RDF can diminish significantly using the spacer-defined patterning technique. Further, the impact of RDF in spacer- and resist-defined FinFET structures has been investigated for noise margins of 6-T static random access memories (SRAM). It is concluded that random dopant variations in SRAM performance offer better immunity in the case of spacer-defined FinFETs compared with resist-defined FinFETs.
In aggressively scaled devices, FinFET technology has become more prone to line-edge roughness (LER) induced threshold voltage variability. To explain this challenge, all possible LER-induced fin shape variabilities in spacer-defined patterning (i.e., correlated LER) and resist-defined patterning (i.e., uncorrelated LER) technology have been investigated for 14-nm underlap FinFET using 3-D numerical simulations. All LER-induced VTH variabilities are analyzed in the presence of other intrinsic variability sources, such as random dopant fluctuation (RDF), work function variation (WFV), and oxide thickness variation (OTV). This study reveals that the percentage threshold voltage (VTH) fluctuations of combined effects (RDF, WFV, and OTV) in spacer-defined and resist-defined FinFETs with respect to rectangular FinFET are 2.88% and 8.76%, respectively.