A preponderance of critical levels for the 90-nanometer (nm) process technology node utilize 193 nm lithography. The resist systems used in this processing show a much higher sensitivity to line width slimming at the traditional electron beam energies encountered in Critical Dimension Scanning Electron Microscope (CD SEM) metrology than do previous generations of chemically amplified resists. The uncertainty that results from this undesirable interaction can consume more than the entire process control budget for advanced devices. This paper reports measurements of resist CD uniformity taken with a new CD SEM metrology technology based on ultra low voltage, that significantly reduces the impact of the electron beam on 193 nm resist systems. Over the past several months this technology has been used for 193 nm resist development studies at ARCH Chemicals. Several examples, demonstrating the effectiveness of this new technology using the Yosemite Ultra Low voltage CD SEM will be presented and contrasted against results obtained at higher voltages.
Current realities of tighter process tolerances combined with continued reduction in engineering resources per metrology tool require that every step of controlling a process a be made more efficient. Analyzing the quality of metrolgoy results, from equipment such as CD SEMs, can involve many factors that include image quality, measurement outputs, focus setting, and amplitude of system settings that play a role in the metrology results. The most efficient means of accessing large volumes of data today is via the World Wide Web. This paper provides examples of metrology problem resolutions that were achieved through the use of WWW on-line analysis of CD SEM results. The relational database that contains the measurement results, CD SEM settings, and metrology and pattern recognition images can be accessed from any fab PC, and can also be accessed from any fab PC, and can also be accessed from outside the fab by personnel with proper levels of security. Simple navigation through a web browser and the completeness of the data in the results database greatly improve the efficiency of the metrologist and the quality of the diagnosis, for improved process control and personal productivity.
Proc. SPIE. 5038, Metrology, Inspection, and Process Control for Microlithography XVII
KEYWORDS: Electron beams, Metrology, Contamination, Data modeling, Atomic force microscopy, Scanning electron microscopy, Process control, Critical dimension metrology, Semiconducting wafers, Systems modeling
Resist slimming under electron beam exposure introduces significant measurement uncertainty in the metrology of 193 nm resists. Total critical dimension (CD) uncertainty of up to 10 nm can arise from line slimming through a combination of the line slimming during the initial measurement pass and the variation of line slimming across the wafer. For a 100 nm process, the entire CD error budget, can be consumed by line slimming. This research examines the uncertainty that results from the use of offset techniques to account for resist slimming in the process control of 193 nm resist CDs. The uncertainty associated with such offset techniques can be as great as 10 nm, depending upon the 193 nm resist and landing energy evaluated. Data are presented to demonstrate that 193 nm resist CD features experience line slimming greater than 5 nm at 500 eV landing energy during the initial measurement pass. Further, subsequent measurements demonstrate greatly reduced slimming and as a result are not indicative of the true magnitude of line slimming. Experiments conducted using CD-AFM pre- and post-analysis, demonstrate that ultra low landing energies significantly decrease the line slimming, reducing it to 1 nm or less.
ArF resist slimming under electron beam exposure introduces significant measurement uncertainty in the metrology of 193nm resists. Previous studies have demonstrated the primary effect of electron landing energy on ArF resist line slimming; this work examines the influence of acquisition time, beam blanking, probe current and measurement magnification. This work will demonstrate, in concurrence with other research, that reducing landing energy remains the most effective method for minimizing line slimming of ArF resist under electron beam exposure. However, the other parameters studied can also affect the magnitude of line slimming. This becomes especially important for line edge roughness (LER) measurements which require a greater total dose be imparted to the sample to maintain measurement precision. Control over all acquisition parameters is essential to achieve accurate and repeatable LER measurements.
Achieving CD control for sub-100 nm processes will be challenging due to the low-k1 regime that optical patterning approaches will be required to work in. New challenges are expected to arise related to new lithography tools, photoresists, reticle types, and in some cases multiple exposures per layer. This work examines the intra-field CD variations for a range of sub-100 nm resist features patterned by chromeless phase-shift 248-nm lithography. One significant advantage of this patterning technique is that the resist CD's are a function of the exposure dose. This provides the ability to examine the CD variations of a range of linewidths in a single experiment without relying on reticle pattern scaling to determine the linewidth printed on the wafer. In addition to exploring CD control vs feature size, we also examine the full-field depth of focus for these features.
This work looks at the application of chromeless phase-shift masks to sub-100 nm gatelength SOI transistor fabrication. The double-exposure technique of Numerical Technologies is extended to the chromeless-edge case. Two masks are used in this method. The first is a darkfield mask with chromeless edges defining the minimum geometry gates and the second is a binary blockout mask which also patterns the larger gate features. This approach provides considerably enhanced resolution performance compared with alternating aperture while still preserving good process latitudes. The chromeless mask fabrication approach is discussed. A simple, single step dry etch is used with no minimum geometry features, thus simplifying mask fabrication. We employed an 0.6 NA, DUV tool for this work together with commercially available resist and anti-reflection layers. Lithography results for k<SUB>1</SUB> factors down to 0.10 and 0.3 are presented. This corresponds to CDs of 40 nm and 125 nm on our Canon EX-4, 248nm stepper. Excellent pattern transfer into polysilicon was achieved using a high density plasma etch process producing gate features down to 25 nm linewidths. We discuss the application of this method to the fabrication of sub-100 nm gate-length fully-depleted SOI CMOS transistors. We have fabricated SOI CMOS transistors with excellent short channel behavior down to 50 nm physical gate lengths. This method enables the development of deep sub-100 nm gate length CMOS technologies using standard 248- nm exposure sources.
In this work, we explore the application of attenuated phase-shift masks (APSM) to sub-0.18 micrometers logic patterning. Particular attention is paid to proximity effects and the common process corridor between dense and isolated features, a key challenge of logic-level lithography. Using PROLITH simulation, we evaluate APSM performance as a function of mask transmission and stepper illumination mode. The optimum process window was found for weak quadrupole illumination. Experimental results were obtained using a test mask consisting of sub-0.25 micrometers L/S Lbar patterns with various pitch values. We compared the case of a 6 percent APSM mask with weak quadrupole illumination to a standard chrome mask with conventional illumination. Properly optimized, APSM can add significant process latitude for sub-0.18micrometers logic features and may enable 130 nm logic node lithography on standard 248 nm exposure tools.