Both the active column sensor (ACS) pixel sensing technology and the PVS-Bus multiplexer technology have been applied to a color imaging array to produce an extraordinarily high resolution, color imager of greater than 8 million pixels with image quality and speed suitable for a broad range of applications including digital cinema, broadcast video and security/surveillance. The imager has been realized in a standard 0.5 μm CMOS technology using double-poly and triple metal (DP3M) construction and features a pixel size of 7.5 μm by 7.5 μm. Mask level stitching enables the construction of a high quality, low dark current imager having an array size of 16.2 mm by 28.8 mm. The image array aspect ratio is 16:9 with a diagonal of 33 mm making it suitable for HDTV applications using optics designed for 35 mm still photography. A high modulation transfer function (MTF) is maintained by utilizing micro lenses along with an RGB Bayer pattern color filter array. The frame rate of 30 frames/s in progressive mode is achieved using the PVS-Bus technology with eight output ports, which corresponds to an overall pixel rate of 248 M-pixel per second. High dynamic range and low fixed pattern noise are achieved by combining photodiode pixels with the ACS pixel sensing technology and a modified correlated double-sampling (CDS) technique. Exposure time can be programmed by the user from a full frame of integration to as low as a single line of integration in steps of 14.8 μs. The output gain is programmable from 0dB to +12dB in 256 steps; the output offset is also programmable over a range of 765 mV in 256 steps. This QuadHDTV imager has been delivered to customers and has been demonstrated in a prototype camera that provides full resolution video with all image processing on board. The prototype camera operates at 2160p24, 2160p30 and 2160i60.
A family of monochrome, high-speed linear imagers has been developed with each device to be available as a single chip fabricated using a standard commercially available CMOS process. Currently, the 2048 pixel device has been fabricated using a 0.5-micron CMOS process and its architecture, functionality and performance is described. The family of imagers features a unique combination of high functional integration, very high speed, low dark current, high sensitivity and high pixel-to-pixel uniformity. The pixels are 7.0 microns by 7.0 microns and have 100 percent fill factor. The high pixel-pixel uniformity is made possible by using low dark current pixels, a correlated double sampler circuit per pixel and a fully differential video bus. High functional integration is enabled by on-chip logic that is provided to minimize support circuitry and simplify application. Included are several exposure modes that provide full-frame electronic shutter, independent control of integration time and simultaneous integration and read-out. Only 5 volts DC and clock signal running at twice the desired pixel rate are required for basic operation. Low dark current and high sensitivity result from a novel pixel and low-noise preamplifier structure. A novel video multiplexing structure provides the very high read-out speed of 60 Mpixel/sec per 2048 pixel segment while sustaining an MTF of 50 percent at 35 line pairs per millimeter.
The University of Connecticut Health Center and Xicon Technologies, LLC have been developing a high speed/high resolution x-ray detector called the XEBIT (X-ray sensitive Electron Beam Image Tube). The XEBIT is a direct conversion image detector that uses Thallium Bromide as the x-ray photoconductor. thallium bromide is a high Z material with a linear attenuation coefficient of 28.11 cm<SUP>-1</SUP> at 60 keV. This high stopping power results in a quantum efficiency in excess of 50% at 60 keV for 300 micron thick layers. The XEBIT has far superior contrast resolution with over 50 percent modulation at 5 line pairs per millimeter and does not suffer from veiling glare. This paper is a report on the works in progress of the XEBIT development, which s near clinical trials.
The development of an acousto-optic null steering processor for radar ECCM applicaiton is reviewed. The general problem to be solved by this special purpose signal processor is discussed and the advantages of the acousto-optic approach are given. Processor architecture, AO/EO component selection, and experimental discoveries are described. Measurements of the laboratory breadboard model's performance for a variety of multipath and non-multipath signals are also covered. Limitations of the current breadboard model and future directions are discussed.
The development of an acousto-optic null steering processor for radar ECCM application is reviewed. The general problem to be solved by this special purpose signal processor is discussed and the advantages of the acousto-optic approach are given. Processor architecture, AO/EO component selection, and experimental discoveries are described. Measurements of the laboratory breadboard model's performance for a variety of multipath and non-multipath signals are also covered. Limitations of the current breadboard model and future directions are discussed.
After reviewing the function of a Multiple Sidelobe Canceler in a typical radar application and providing an overview of the goals and architecture of the Acousto-Optic Null Steering Processor program, this paper describes the hardware configuration of the breadboard model and reports the performance of this system to date. Significant design issues and experimental observations are discussed. Some of these design issues have been discovered during breadboard evaluation; others were predicted by simulation and have been verified experimentally. This paper concludes by identifying those areas where the greatest potential for performance improvement lies.
The Acousto-Optic Null Steering Processor (AONSP) is an acousto-electro-optic implementation of a radar multiple sidelobe canceler (MSLC) addressing wideband jamming and multipath. The flowdown of requirements from adaptive canceler performance to hardware configuration is the subject of this paper. The development program is sponsored by DARPA and Rome Laboratory.
An analog optical signal processor has been developed to implement the function of antenna sidelobe interference cancellation. The architecture, which includes optical correlators with Bragg cell input, an optical time modulator, and an optical spatial integrator, performs an operation which is equivalent to the multiple-loop Howells-Applebaum Least Mean Square (LMS) algorithm. This implementation offers the potential for cancelling multiple correlated interference signals (i.e., direct path and multipath interference signals) with an appropriate number of auxiliary antennas. A previous report described single frequency CW tests of such a processor. Preliminary tests with wide-band waveforms and the special test instrumentation developed to perform these tests are described in this paper.