A more precise and accurate method of quantifying line end effects on binary photomasks becomes necessary as reticle features continue to decrease in size. A new methodology for measuring and evaluating line ends was developed. By performing multiple step-wise measurements across a single line end feature using a fixed-width region of interest, a simulated representation of the line end profile could be generated. A high n-order polynomial fit was then applied to the resultant data set and a minimum line end value was extrapolated. This methodology reduced the measurement error directly caused by the region-of-interest (ROI) placement and sizing while, at the same time, it improved the accuracy and precision of the measurement. The generated line end profiles may be further used for modeling, simulation, or characterization.
High-speed production of semiconductor devices demands in-line wafer metrology on a minimum number of sample points. If this data does not represent the average chip feature size, then an in-line monitor may indicate that a wafer is right on target. However, at end-of-line testing, the electrical parameters, incorporating all features within the chip, may be found shifted away from target. This paper presents a solution which increases wafer critical dimension targeting efficiency while notably relaxing the traditional mean-to-target reticle specification. By embedding ART (Average Representative Targeting) Structures into the reticle scribe, Reticle Engineering at LSI Logic leverage off the ability to adjust wafer exposure dose to compensate for off target reticle CDs. The novel targeting structure described in this paper assures average wafer CDs within 2.5 nm of target while effectively doubling the acceptable range for a standard mean to target reticle specification.
We present a comparison of line edge roughness on wet and dry etched reticles manufactured at the same mask shop. These measurements were taken on a Leica LWM250, and compare identical features on both masks. A 30% improvement in line edge quality was seen on the dry etched plates. Data supporting these results is presented.
ASIC companies face consistent pressure to reduce cost, improve quality, and decrease the time to production for reticles used in integrated circuit fabrication. In order to meet these objectives, the Reticle Engineering group at LSI Logic has developed an efficient and accurate defect control methodology. Three case studies in this paper highlight a unique defect management strategy. The scenarios describe rejecting a reticle to the vendor, releasing a reticle to the fab while deeming a defect innocuous, and tracking a reticle through production with a known yield impacting defect. The defect management solutions highlighted in this paper include a web based defect classification and disposition system to supplement the Lasertec MD2000 die to die inspection tool, virtual inking of affected die, and a production process flow for defect verification on silicon wafer prints. Quantitative results are shown, illustrating the elimination of vendor induced repeaters, improvements in baseline defect density, and improved cycle time for defect analysis and inspection flows.