We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm
technology node by integrating it into standard semiconductor process flows because we believe that device integration
exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In
this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and
first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art
defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably
higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV
lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the
0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.
The development of Double-Patterning (DP) techniques continues to push forward aiming to extend the immersion
based lithography below 36 nm half pitch. There are widespread efforts to make DP viable for further scaling of
semiconductor devices. We have developed Develop/Etch/Develop/Etch (DE2) and Double-Expose-Track-Optimized
(DETO) techniques for producing pitch-split patterns capable of supporting semiconductor devices for the 16 nm and 11
nm nodes. The IBM Alliance has established a DETO baseline, in collaboration with ASML, TEL, CNSE, and KLATencor,
to evaluate the manufacturability of DETO by using commercially available resist systems. Presented in this
paper are the long-term performance results of these systems relevant to defectivity, overlay, and CD uniformity.
We describe progress in implementation of blur-based resolution metrics for EUV photoresists. Three sets of blur
metrics were evaluated as exposure-tool independent comparison methods using the Sematech-LBNL EUV microexposure
tool (MET) and ASML α-Demo Tool (ADT) full-field EUV scanner. For the two EUV resists studied here,
deprotection blurs of 15 nm are consistently measured using blur estimation methods based on corner rounding, contact
hole exposure latitude, and process window fitting using chemical amplification lumped parameter models. Agreement
between methods and exposure tools appears excellent. For both resists, SRAM-type lithographic diagnostic patterns at
80 nm pitch are only modestly sensitive to OPC blur compensation and display robust printability (RELS ~ ILS near 50
μm-1 for multiple trench geometries) on the ASML ADT. These findings confirm the continuing utility of blur-based
metrics in a) guiding resist selection for use in EUV process development and integration at the 22 nm logic node and
below, and b) providing an exposure-tool independent set of metrics for assessing progress in EUV resist development.
As our ability to scale lithographic dimensions via reduction of actinic wavelength and increase of numerical
aperture (NA) comes to an end, we need to find alternative methods of increasing pattern density. Double-Patterning
techniques have attracted widespread interest for enabling further scaling of semiconductor devices. We have developed
DE2 (develop/etch/develop/etch) and DETO (Double-Expose-Track-Optimized) methods for producing pitch-split
patterns capable of supporting 16 and 11-nm node semiconductor devices. The IBM Alliance has established a DETO
baseline in collaboration with KT, TEL, ASML and JSR to evaluate commercially available resist-on-resist systems. In
this paper we will describe our automated engine for characterizing defectivity, line width and overlay performance for
our DETO process.
Double patterning is considered the most viable option for 32- and 22-nm complementary metal-oxide semiconductor (CMOS) node development and has seen a surge of interest due to the remaining challenges of next-generation lithography systems. Most double patterning approaches previously described require intermediate processing steps (e.g., hard mask etching, resist freezing, spacer material deposition, etc.). These additional steps can add significantly to the cost of producing the double pattern. Alternative litho-only double patterning processes are investigated to achieve a composite image without the need for intermediate processing steps. A comparative study between positive–negative (TArF-P6239+N3007) and positive–positive tone (TArF-P6239+PP002) imaging is described. In brief, the positive–positive tone approach is found to be a superior solution due to a variety of considerations.
In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to
produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography
to pattern the first interconnect level (metal 1).
This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing
effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield
EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The
CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip
(product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity
of 3.8 mJ/cm2, providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good
CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as
evidenced by electrical test results.
Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to
have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.
With 32nm and 22nm feature size node in the near future, Double patterning type processing will be in
mainstream device manufacturing in most cutting edge Fabrication facilities. These type of processes
requires cooperation between the litho cell and the other processing modules. In a collaboration
between ASML and TEL we have developed a integrated solution to image 30nm Contacts. We
describe a novel technique to achieve a geometric shrink from a starting geometry of 65nm down to the
final feature size of 30nm for each of the two contact images Processing 2 images separately could
produce two distinct populations for alignment and critical dimensions. We will show the ability to
image 65nm contacts on a 130nm pitch with acceptable process windows and then apply the novel CD
shrink process to shrink the 65nm contacts to 30nm final dimension. The second level of contacts is
imaged in between the 1st set of contacts allowing us to image a 32nm ½ pitch contact pattern.
We show the ability to Image 2 separate sets of contacts using a split clip layout with a single
distribution for critical output parameters. We address the following process challenges:
1) Overlay capability across the slit and across the field.
2) Critical Dimension capability across the slit and across the Field.
3) Sidewall angle integrity with acceptable process window.
Using the novel CD shrink process TEL has developed and imaging capability of the an ASML 1700i
TWINSCAN, we can achieve a double pattern contact process with acceptable process capability.
A thick positive chemical amplified DUV photoresist, Shipley UV 25, is designed with high transparency (0.18AU) for implant layer application. Comparing with traditional Novolak I-line implant layer resists high aspect ratio and fast photospeed of UV 25 is demonstrated. Lithographic results show that UV 25 has excellent coating capability up to 3 microns thick, with excellent photospeed and good overall lithographic performance for various features. Process optimizations of UV 25 for various features are investigated. The results indicate that the temperatures of softbake and post exposure-bake play very important roles in improving the process windows. We have found that high softbake for better annealing and solvent removal is critical, and the best lithographic process is typically at PEB temperatures lower than the softbake temperature (at least 20 degrees Celsius lower). The process with a high softbake temperature and a low PEB temperature significantly improved overall process window. In addition, PED stability with an optimal baking process is also studied.