A monolithically integrated optical receiver in 0.6 μm bipolar complementary metal oxide semiconductor (BiCMOS) technology with 45 channels, each working at a data rate of 3.125 Gbit/s, is described. The optical receiver uses integrated pin photodiodes with a diameter of 90 μm. This parallel optical silicon receiver is capable of operating at 100°C. The parallel optical receiver consumes less than 950 mW in total and each of its channels achieve an optical sensitivity of −17.5 dBm at 850 nm wavelength and a bit error ratio of 10−9.
A vertical pin photodiode with a thick intrinsic layer is integrated in a 0.5-μm BiCMOS process. The reverse bias of the photodiode can be increased far above the circuit supply voltage, enabling a high-drift velocity. Therefore, a highly efficient and very fast photodiode is achieved. Rise/fall times down to 94 ps/141 ps at a bias of 17 V were measured for a wavelength of 660 nm. The bandwidth was increased from 1.1 GHz at 3 V to 2.9 GHz at 17 V due to the drift enhancement. A quantum efficiency of 85% with a 660-nm light was verified. The technological measures to avoid negative effects on an NPN transistor due to the Kirk effect caused by the low-doped I-layer epitaxy are described. With a high-energy collector implant, the NPN transit frequency is held above 20 GHz. CMOS devices are unaffected. This photodiode is suitable for a wide variety of high-sensitivity optical sensor applications, for optical communications, for fiber-in-the-home applications, and for optical interconnects.
We present the state of the art of integrated silicon photodetectors and circuits by concentrating on the progress in the
last decade. Especially three highlights will be presented in more detail.
In this paper a vertical pin-photodiode in a 0.6μm BiCMOS technology, consisting of an n-buried cathode, an n<sup>-</sup> epi
layer, and a p<sup>+</sup> anode will be discussed. The measured responsivities for different wavelengths are 0.33A/W @ 850nm
and 0.46A/W @ 660nm, respectively. Really outstanding is the reached speed of the photodiodes. The -3dB cut-off
frequencies of these 50x50μm<sup>2</sup> diodes are up to 2.1GHz @850nm light and up to 3GHz @660nm light, depending on the
reverse bias voltage.
This high performance photodiode allows the competition of pure silicon optoelectronic integrated circuits (OEICs) even
with GaAs OEICs. A silicon OEIC reaches at 2.5Gb/s<sup>1</sup> a higher sensitivity than a GaAs OEIC<sup>2</sup>. It also consumes less
power and a remarkably smaller chip area.
Massive parallel integration of optical receivers enables an extremely high total data rate. A new OEIC consisting of 45
parallel channels with a data rate of 3Gb/s @850nm each allows an overall data rate of 135Gb/s.
The presented paper describes a 10 Gbps optical receiver. The transimpedance amplifier (TIA) is realized in standard
0.35 μm SiGe BiCMOS technology. The main novelty of the presented design - investigated in the European
Community project HELIOS - is the hybrid connection of the optical detector. The used Germanium photodetector will
be directly mounted onto the receiver.
A model of the relevant parasitics of the photodetector itself and the novel connection elements (micropads, metal vias
and metal lines) is described. Based on this photodetector model an optical receiver circuit was optimized for maximum
sensitivity at data rates in the range of 10 Gbps.
The design combines a TIA and two limiting amplifier stages followed by a 50 Ω CML-style logic-level output driver.
To minimize power supply noise and substrate noise, a fully differential design is used. A dummy TIA provides a
symmetrical input signal reference and a control loop is used to compensate the offset levels. The TIA is built around a
common-emitter stage and features a feedback resistor of 4.2 Ω. The total transimpedance of the complete receiver
chain is in the range of 275 kΩ. The value of the active feedback resistor can be reduced via an external control voltage
to adapt the design to different overall gain requirements. The two limiting amplifier stages are realized as differential
amplifiers with voltage followers. The output buffer is implemented with cascode differential amplifiers. The output
buffer is capable of driving a differential 50Ω output with a calculated output swing of 800mVp-p.
Simulations show an overall bandwidth of 7.2 GHz. The lower cutoff frequency is below 60 kHz. The equivalent input
noise current is 408 nA. With an estimated total photodiode responsivity of 0.5 A/W this allows a sensitivity of around -
23.1 dBm (BER = 10-9). The device operates from a single 3.3 V power supply and the TIAs and the limiting amplifier
consume 32 mA.
This work presents two types of optical receivers with large-diameter photodiodes. Both are optoelectronic integrated circuits (OEICs) realized in 0.6μm BiCMOS Si technology integrating PIN photodiode, transimpedance amplifier (TIA) and output circuit on chip. The two circuits are an optocoupler with a photodiode diameter of 780μm and a rise- and falltime of 5ns and 4.9ns respectively at 850nm light and a plastic optical fiber (POF) receiver with a photodiode diameter of 500μm and upper -3dB cut-off frequencies of 165MHz at 660nm light and 148MHz at 850nm light. The measured rise- and falltime of the POF receiver was 1.78ns and 2.45ns at 660nm light and 1.94ns and 2.5ns at 850ns, respectively. The presented results combine the advantage of easier handling of large-diameter photodiode receivers and high performance.
Optoelectronic integrated circuits (OEICs) offering high bandwidth and high sensitivity as well are needed for the pickups of optical storage systems of the next generation, such as Blu-Ray or HDDVD. High bandwidth is necessary to enable high data transfer rates between the disk and the processing device, and high sensitivity allows to operate at low optical power and to deal with the lower efficiency of the photodiodes for blue light. Two methods will be presented to increase the bandwidth of the OEIC while maintaining high sensitivity. The first approach reduces the parasitic capacitance by placing the feedback resistor in a low-doped region. By this way the parasitic capacitance of the resistor is combined in series with the small depletion-layer capacitance of the low-doped region, which results in a drastically reduced effective capacitance. Using this method the 3dB-frequency of a standard one-stage transimpedance amplifier is increased by 55% from 67MHz to 104MHz. In the second approach the feedback resistor is replaced by a network that consists of two resistive voltage dividers that are coupled via a capacitor. Using such a capacitive-coupled voltage divider (CCVD) the feedback path is split into a low- and a high-frequency path and the effective band-limiting RC-constant is reduced. A bandwidth of 378MHz could be achieved. With a measured transimpedance of 212kΩ this results in a GBW of 80.3THzΩ.
For digital versatile disk (DVD) applications, amplifiers with high bandwidth and high sensitivity in the red spectral range are required. The presented optoelectronic integrated circuit (OEIC) achieves a bandwidth of 265MHz and a transimpedance of 210kΩ due to an advanced feedback network. This is an improvement by a factor of 4 compared to the same amplifier with a simple feedback resistor.
Currently two very interesting trends in design of optical receivers can be observed. The first is to realize optical receivers in deep-sub-μm CMOS technology and to integrate them in analog-digital systems-on-a-chip (SoC). The second even much more innovative trend is to integrate voltage-up-converters (VUCs) in optoelectronic integrated circuits (OEICs) to increase the bandwidth and data rate, whereby only the chip voltage supply is necessary. The properties of deep-sub-µm CMOS optical receivers and of sub-μm OEICs with respect to current consumption, noise, and chip area will be compared. For both trends a new design each and measured results will be presented. The first example is a burst-mode receiver in digital 0.18μm CMOS technology with sensitivities better than -28 dBm and -22 dBm at data rates of 622Mb/s and 1.25Gb/s, respectively, for a bit error rate of 10-10 each. These values compare to sensitivities of -24.5 dBm and -24.1 dBm, respectively, of a 0.6μm BiCMOS OEIC. For implementation of the burst-mode receiver in an analog-digital SoC, a differential circuit is chosen. Another example is an OEIC in 0.6μm BiCMOS technology with an integrated VUC, which generates a bias voltage of 16V for the integrated photodiode from the chip supply voltage of 5V. Due to the VUC, the data rate for the given technology is increased from 50Mb/s to 1.5Gb/s. The dependence of the receiver sensitivity and of the maximum photocurrent on the VUC clock-frequency will be shown. The VUC-OEIC represents a complete SoC consisting of sensor, analog and digital part. Aspects of substrate noise coupling from the digital part into the photodiode and amplifier are discussed.