This paper presents a proposal of a protocol for communication between the read-out integrated circuit for the STS
(Silicon Tracking System) and the Data Processing Board (DPB) at CBM (Compressed Baryonic Matter) experiment at
FAIR, GSI (Helmholtzzentrum fuer Schwerionenforschung GmbH) in Germany. The application background, objectives
and proposed solution is presented.
Hybrid pixel detectors working in a single photon counting mode are very attractive solutions for material science and
medical X-ray imaging applications. Readout electronics of these detectors has to match the geometry of pixel detectors
with an area of readout channel of 100 μm × 100 μm (or even less) and very small power consumption (a few tens of
μW). New solutions of readout ASICs are going into directions of better spatial resolutions, higher data throughput and
more advanced functionality. We report on the design and measurement results of two pixel prototype ASICs in
nanometer technology and 3D technology which offer fast signal processing, low noise performance and advanced
functionality per single readout pixel cell.
This paper presents the prototype detector readout electronics for the STS (Silicon Tracking System) at
CBM (Compressed Baryonic Matter) experiment at FAIR, GSI (Helmholtzzentrum fuer
Schwerionenforschung GmbH) in Germany. The emphasis has been put on the strip detector readout
chip and its interconnectivity with detector. Paper discusses the impact of the silicon strip detector and
interconnection cable construction on the overall noise of the system and architecture of the TOT02
readout ASIC. The idea and problems of the double-sided silicon detector usage are also presented.
The Application Specific Integrated Circuits (ASICs) are widely used for the detector readout in the High Energy Physics (HEP) environment. The ASICs have to work in high radiation environment and provide the basic parallel signal processing from a huge number of detector channels, including substantial data compression. The reliability of the ASICs is a critical issue for the data taking eficiency of the whole system. In the paper the examples of several ASIC design blocks are given with a special focus on the features providing reliability in radiation environment. The problems of the architecture choice, ASIC synchronization, and redundancy is discussed in detail. These aspects of design will be presented on the example of two chips, ABCD and DTMROC dedicated to the one of the general purpose experiments on Large Hadron Collider, ATLAS. The ABCD is the ASIC for the readout of the Semiconductor Tracker (SCT) detector designed using the 0.8 μm BiCMOS technology, and the DTMROC is the readout chip for the Transition Radiation Tracker (TRT) detector, designed using 0.25 μm CMOS technology.
The radiation hardness is a critical issue for a number of ASIC applications. The ASICs used in space, physics experiments or in medical instrumentations have to deal with the radiation and its effects. The paper gives a short overview of the radiation-induced effects in the CMOS devices and presents design and system aspects of the ASIC radiation hardening. Examples of chips designed for heavy radiation environment are presented.