With photolithography as the fundamental patterning step in the modern nanofabrication process, every wafer within a semiconductor fab will pass through a lithographic apparatus multiple times. With more than 20,000 sensors producing more than 700GB of data per day across multiple subsystems, the combination of a light source and lithographic apparatus provide a massive amount of information for data analytics. This paper outlines how data analysis tools and techniques that extend insight into data that traditionally had been considered unmanageably large, known as adaptive analytics, can be used to show how data collected before the wafer is exposed can be used to detect small process dependent wafer-towafer changes in overlay.
Shrinking pattern sizes dictate that scanner-to-scanner variations for HVM products shrink proportionally. This paper shows the ability to identify (a subset of) root causes for mismatch between ArF immersion scanners using scanner metrology. The root cause identification was done in a Samsung HVM factory using a methodology (Proximity Matching Budget Breakdown or PromaBB) developed by ASML. The proper identification of root causes<sup>-1</sup> helps to select what combination of scanner control parameters should be used to reduce proximity differences of critical patterns while minimizing undesirable side effects from cross-compensation. Using PromaBB, the difference between predicted and measured CD mismatch was below 0.2nm. PromaBB has been proposed for HVM implementation at Samsung in combination with other ASML fab applications: Pattern Matcher Full Chip (PMFC), Image Tuner and FlexWave.
Strong resist shrinkage effects have been widely observed in resist profiles after negative tone development (NTD) and therefore must be taken into account in computational lithography applications. However, existing lithography simulation tools, especially those designed for full-chip applications, lack resist shrinkage modeling capabilities because they are not needed until only recently when NTD processes begin to replace the conventional positive tone development (PTD) processes where resist shrinkage effects are negligible. In this work we describe the development of a physical resist shrinkage (PRS) model for full-chip lithography simulations and present its accuracy evaluation against experimental data.
Scanner matching based on CD or patterning contours has been demonstrated in past works. All of these published works require extensive wafer metrology. In contrast, this work extends a previously proposed optical pattern matching method that requires little metrology by adding the component requirements and the procedure for creating an automation flow. In a test case, we matched an ASML XT:1900i using a DOE to an ASML NXT:1950i scanner using FlexRay. The matching was conducted on a 4x nm process test layer as a development vehicle for the 2x nm product nodes. The paper summarizes the before and after matching data and analysis, with future opportunities for improvements suggested.
Traditional scanner matching methods have been based in 1D proximity matching targets
and the use of wafer-based CD metrology to characterize both the initial mismatch as
well as the sensitivity of CDs to scanner tuning knobs.
One such method is implemented in ASML Pattern Matcher, which performs a linear
optimization based on user provided CD sensitivities and pre-match data. The user
provided data usually comes from wafer exposures done at multiple scanner illumination
conditions measured with CD-SEM. In the near future ASML plans to provide the
capability to support YieldStar CD data for Pattern Matcher which will collect CD data
with higher precision and much faster turn-around-time that CD-SEM.
Pattern Matcher has been used successfully in multiple occasions. Results for one such
occasion are shown in Figure 1 which presents the through pitch mismatch behavior of
one ASML XT:1400F with respect to an ASML XT:1400E for a 32nm contact layer.
Proximity matching is a common activity in the wafer fabs<sup>1,2,3</sup> for purposes such as
process transfer, capacity expansion, improved scanner yield and fab productivity. The
requirements on matching accuracy also become more and more stringent as CD error
budget shrinks with the feature size as technology advances. Various studies have been
carried out, using scanner knobs including NA, inner sigma, outer sigma, stage tilt,
ellipticity, and dose. In this paper, we present matching results for critical features of a
logic device, between an ASML XT:19x0i scanner and an XT:1700i (reference),
demonstrating the advantage of freeform illuminator pupil as part of the adjustable
knobs to provide additional flexibility. We also present the investigation of a novel
method using lens manipulators for proximity matching, effectively injecting scalar
wavefront to an XT:19x0i to mimic the behavior of the XT:1700i lens.
Scanner matching based on wafer data has proven to be successful in the past years, but its adoption into production has
been hampered by the significant time and cost overhead involved in obtaining large amounts of statistically precise
wafer CD data. In this work, we explore the possibility of optical model based scanner matching that maximizes the use
of scanner metrology and design data and minimizes the reliance on wafer CD metrology.
A case study was conducted to match an ASML ArF immersion scanner to an ArF dry scanner for a 6Xnm technology
node. We used the traditional, resist model based matching method calibrated with extensive wafer CD measurements
and derived a baseline scanner manipulator adjustment recipe. We then compared this baseline scanner-matching recipe
to two other recipes that were obtained from the new, optical model based matching method. In the following sections,
we describe the implementation of both methods, provide their predicted and actual improvements after matching, and
compare the ratio of performance to the workload of the methods. The paper concludes with a set of recommendations
on the relative merits of each method for a variety of use cases.
Given the continually decreasing k1 factor and process latitude in advanced technology nodes, it is important to fully
understand and control the variables that impact imaging behavior in the lithography process. In this joint work between
TSMC and ASML, we use model-based simulations to characterize and predict the imaging effects of these variables
and to fine-tune the scanner settings based on such information in order to achieve optimal printing results on a perreticle
basis. The scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for
accurate model construction. Simulations based on the calibrated model are subsequently used to predict the wafer
impact of changes in tunable scanner parameters for all critical patterns in the product. The critical patterns can be
identified beforehand, either experimentally on wafer, mask or through model simulations. A set of optimized scanner
setting offsets, known as a "scanner tuning recipe" is generated to improve the imaging behavior for the critical patterns.
We have demonstrated the efficacy of this methodology for multiple-use cases with selected ASML scanners and TSMC
processes and will share the achieved improvements on defect reduction and yield improvements.
Given the decrease in k1 factor for 65nm-node lithography technology and beyond, it is increasingly important to
understand and control the variables which impact scanner imaging behavior in the lithography process. In this work, we
explore using model simulations to characterize and predict imaging effects of these variables, and then based on such
information to fine-tune the scanner settings to obtain printing results optimally matched to a reference scanner. The
scanner modeling makes use of detailed scanner characteristics as well as wafer CD measurements for accurate model
construction. To identify critically mismatched patterns on a production layout, we employ the fast full-chip simulation
capability provided by Brion's Tachyon servers. Tachyon simulations are also used to predict wafer impacts of changes
in tunable scanner parameters. A set of optimized scanner variable offsets, called a "scanner tuning recipe", is generated
to minimize overall imaging mismatch between two scanners. As a proof-of-concept, we have carried out scanner tuning
procedures on selected ASML scanners. The results show improvements more than 20% on CD offset RMS values for
2D line-end patterns, production layout patterns, and the mismatched patterns identified with the full-chip simulation.
Improvements on wafer-acceptance-test results and production yield on the to-be-tuned scanner are also observed.
Double Patterning (DP) is one of the main enabling technologies for expanding Photolithography
beyond 40nm technology node. Geometrical pitch split is the core of DP.
It is known and reviewed in this paper that not all sub-resolution layouts can be successfully split to
two DP masks, so a method for early Design for Manufacturability (DfM) check is strongly required.
New accurate, efficient and Litho-aware methods for DP also minimize number of split errors and
"false alarms" typical for Rule-Based Mask Data Preparation for Double Patterning.
In this paper we proposed the topological approach (Model assisted Topological Rules Check,
MTRC) to the pitch decomposition for Double Patterning based on Litho process modeling and real
Litho resolution of a process.
This method allows to find features below a resolution limit of a process and automatically sort them
between DP-friendly and DP-unfriendly (DfM check for requiring redesign, "native conflicts", NC)
cases. MTRC helps to improve DP-unfriendly designs in optimal way at early stage and avoid costly
The second part of the paper explains the Model based DP pitch decomposition algorithm based on
layout printability. It performs accurate and efficient split of various patterns with k1<0.25 to two
masks with k1>0.25 as an integrated part of the Mask Data Preparation flow.
The developed algorithm of Model based DP pitch decomposition allows error-free split of patterns
below the resolution limit of the Litho system to two DP masks with sufficient printability confirmed
by simulations and MTRC.
The analysis of performance of the complex MB DP split approach mentioned above was performed
on a selection of clips representing generic designs and typical Flash, DRAM, SRAM and Logic
To fulfill Moore's law the R&D stage of 3x nm HP nodes will have to be reached in 2008. Conventional DUV
immersion technology is resolution limited to half pitch values exceeding 40 nm. Double Patterning Technology (DPT)
is a major candidate to reach the 3x nm node in time. Geometrical pattern split, doubling the pitch, is one of the major
steps of DPT. We present a feasibility study of the Rule Based (RB) DPT approach to pattern splitting based on a
representative and reviewed selection of clips and full-mask designs.