Video imagery can be acquired from aerial, terrestrial and marine based platforms and has been exploited for a range of
remote sensing applications over the past two decades. Examples include coastal surveys using aerial video, routecorridor
infrastructures surveys using vehicle mounted video cameras, aerial surveys over forestry and agriculture,
underwater habitat mapping and disaster management. Many of these video systems are based on interlaced, television
standards such as North America's NTSC and European SECAM and PAL television systems that are then recorded
using various video formats. This technology has recently being employed as a front-line, remote sensing technology for
damage assessment post-disaster.
This paper traces the development of spatial video as a remote sensing tool from the early 1980s to the present day. The
background to a new spatial-video research initiative based at National University of Ireland, Maynooth, (NUIM) is
described. New improvements are proposed and include; low-cost encoders, easy to use software decoders, timing issues
and interoperability. These developments will enable specialists and non-specialists collect, process and integrate these
datasets within minimal support. This integrated approach will enable decision makers to access relevant remotely
sensed datasets quickly and so, carry out rapid damage assessment during and post-disaster.
KEYWORDS: Human-machine interfaces, Transmitters, Modulation, Computing systems, Receivers, Linear filtering, Telecommunications, Software development, Standards development, Global system for mobile communications
A modular testbed for use in developing software defined radio is documented in this paper. The testbed is focused on the 2.4 GHz ISM band but may be used at other frequencies. An RF transceiver with variable transmit/receive frequencies and bandwidths is provided. It provides the capability to support many modulation schemes and standards such as GSM, UMTS, IEEE 802.11b and parts of the IEEE802.16 standards. It performs the RF functions of the radio, with the other PHY and MAC layer functions such as equalisation and error-coding being performed by a host computer. It communicates with the host computer system through a USB2 interface allowing data rates of up-to 60Mbytes a second. An API is used for communication with the host computer system allowing for modulation/demodulation and coding/decoding in software on the host system and reconfiguration of the radio system.
In this paper a modified relaxation oscillator is proposed as the core of an analog to digital modulator for on chip signal extraction for test. The architecture uses digital current source generation and digital switching in place of active circuitry. The resulting design allows for high input sensitivity, robustness to component variation while occupying little silicon area. This paper provides solutions on the main challenges in implementing this modulator and how it may be integrated with a digital based tester.
With the current trend towards software defined radio, several candidate architectures for the analog receiver front-end have been presented. A common proposal for software defined reconfigurable radio is to develop a wideband ADC and utilise this for capturing a large segment of the spectrum. This would enable the subsequent signal processing operations of channel selection and data extraction to be carried out by a digital processor. This would allow the radio to be reconfigured by simply changing the software. In analysis of these systems, powerful neighbouring signals, or blockers, are considered but it has been conveniently assumed that suitable dynamic range will be available at the ADC. This is an acceptable assumption in narrowband systems where automatic gain control and analogue channel select filters can be used, but is not appropriate for a wideband system. In this paper we present an analysis based on bit-error-rates (BER) which shows the effect of blockers in a wideband architecture on the performance of the communication link and on the dynamic range requirements of the ADC.
Presented in this paper is a low power, area efficient pipeline analog-to-digital converter (ADC), utilising a charge summation technique and a switched-capacitor implementation. Utilising switched capacitor, a staircase ramp is produced caused by the switching capacitors and a fixed reference voltage, as opposed to a linear ramp. The advantage of the charge summation technique is the reduction in power usage as the charging time of the capacitors is small so for most of the sample period the circuit is quiescent. The paper presents the use of this architecture as a 14-bit pipelined ADC, which can sample data at a rate of 1 MSps. The pipeline architecture itself is novel as the typical sub-DAC is not required. The signal-to-noise ratio (SNR) of the ADC is improved by using a spatial over-sampling technique, which reduces the thermal noise effect on in the switched capacitor circuit. The effects of opamps finite gain and offset on the linearity of the ramp are reduced by employing a finite gain and offset compensated integrator architecture and through the use of low-resolution pipeline stages. The proposed architecture is a strong candidate for applications demanding high resolution with low power requirements.
In this paper an on-chip method for testing high performance memory devices will be presented. This new technique occupies minimal area and retains the full flexibility of existing methods for the dynamic introduction of new test patterns. This is achieved through microcode test instructions and the associated on-chip state machine. The proposed methodology will enable at-speed testing of memory devices, reducing the overall test time. The relevancy of this work is placed in context with an introduction to memory testing and the techniques and algorithms generally used today. Additionally, we examine the use of fault simulation in methodology evaluation for memory test. Finally we present a prototype design for the implementation of this methodology that incurs minimal test latency and provides a programmable interface to enable varying fault coverage and location patterns.
In this paper a new stable high order Digital Phase Lock Loop (DPLL) design technique is proposed. PLLs of order greater than two display better noise bandwidth, Bl, than classical second order PLLs. However these are not unconditionally stable as in the second order case. This technique uses linear theory to design the DPLL. The stability of the DPLL is guaranteed by placing a restriction on the system gain. This stability boundary is found by transforming the
system transfer function to the Z-domain and plotting the root locus of the LPLL for values of gain where all the system poles lie inside the unit circle. The minimum value of gain where all the poles lie inside the unit circle forms the stability boundary. It is shown that the stability boundary of the LPLL is comparable to the stability boundary of the DPLL. Finally where the above filter design system produces slow lock, gear shifting of the DPLL components is considered. This allows the DPLL to start off with a wide loop bandwidth and switch to the narrow bandwidth once the system has locked.