High-speed digital cameras are progressing rapidly with the development of CMOS image sensor in these few years. In
order to develop a high-speed CMOS industrial digital camera, the CMOS image sensor MI-MV13 is used. The sensor
drive pulse and control timing based on Xilinx Virtex-II Pro FPGA is designed. A novel format of digital image
transporting based on Camera Link data port is defined in this paper. It is implemented 1280 (H) × 1024 (V) SXGA
resolution digital image transported at a high frame rate of 300 fps (frames-per-second) with 5 Pixels 10 bit compatible
Camera Link Medium Configuration. In addition, these functions that adjustments of exposure beginning time, integral
time, AOI (Area of Interest) output and so on, are realized in a FPGA chip. All of the function modules are embedded in
a SOPC (System on a Programmable Chip), and further functions can be easily added to the chip at the second time
development. Experimental results show that the design of driving control timing and data interface in FPGA is suitable
for high-frame rate, low power, intelligent and miniaturization digital video camera.
CCD noises and their causes are analyzed. Methods to control these noises, such as Correlated Double Sampling (CDS), filtering, cooling, clamping, and calibration are proposed. To improve CCD sensor's performances, the IC, called Analog Front End (AFE), integration of CDS, clamping, Programmable Gain Amplifier (PGA), offset, and ADC, which can fulfill the CDS and analog-to-digital conversion, is employed to process the output signal of CCD. Based on the noise control approaches, the idea of chip design of linear CCD drive pulse generator and control interface is introduced. The chip designed is playing the role of (1) drive pulse generator, for both CCD and AFE, and (2) interface, helping to analysis and transfer control command and status information between MCU controller and drive pulse generator, or between global control unit in the chip and CCD/AFE. There are 6 function blocks in the chip designed, such as clock generator for CCD and AFE, MCU interface, AFE serial interface, output interface, CCD antiblooming parameter register and global control logic unit. These functions are implemented in a CPLD chip, Xilinx XC2C256-6-VQ100, with 20MHz pixel frequency, and 16-bit high resolution. This chip with the AFE can eliminate CCD noise largely and improve the SNR of CCD camera. At last, the design result is presented.