In this paper, the hardware implementation of a scheduler with QoS support is presented. The starting point is a
Differentiated Service (DiffServ) network model. Each switch of this network classifies the packets in flows which are
assigned to traffic classes depending of its requirements with an independent queue being available for each traffic class.
Finally, the scheduler chooses the right queue in order to provide Quality of Service support. This scheduler considers
the bandwidth distribution, introducing the time frame concept, and the packet delay, assigning a priority to each traffic
class. The architecture of this algorithm is also presented in this paper describing their functionality and complexity. The
architecture was described in Verilog HDL at RTL level. The complete system has been implemented in a Spartan-3
1000 FPGA device using ISE software from Xilinx, demonstrating it is a suitable design for high speed switches.
A novel variable length packet scheduling algorithm focused on real output queue reference architecture is presented in
this paper. The main features of this packet scheduler development are the Quality of Service (QoS) and variable length
packet support. The packet scheduler supports up to eight traffic classes which can be assigned up to two different
priorities. The bandwidth assigned to any traffic class is configurable. The packet scheduler has been described and
simulated in C++ language under uniform and bursty traffic conditions.
A multidrop backplane based on point-to-multipoint serial links enables interconnection between line cards without requiring a central switch fabric. However, maximum data rate in today's available multidrop serial links is limited to 400Mbps due to signal integrity concerns. In this paper, a novel gigabit multidrop serial link configuration for high-speed digital systems based on broadband power splitters with matching trace impedance, is proposed. Experimental results obtained from implemented prototypes demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data rate of 3.5Gbps.
Nowadays digital networks require architectures based on standards that are implemented independently of the technology. Besides, these network specifications can easily change to include novel services. For these reasons, dominant trends are to design and verify systems at high level, prior to technology mapping. In this paper, a methodology is proposed to obtain a full verified system from an architecture specification. In order to validate this methodology, a system specification document is used as starting point. This specified system is partitioned in average size modules and then each module is described itself in design specification documents, which are the basis of their implementation using Hardware Description Languages (HDL). Each module is verified based on test specification documents generated along with the design specification. Finally, all the modules are interconnected and verified using an automatic test vector generator. Firstly, this approach introduces a method that, independently of the size of the system, improves reliability in the results, and secondly, it documents all the steps performed during the different stages. In order to validate this methodology, SDH (Synchronous Digital Hierarchy) and ATM (Asynchronous Transfer Mode) standards was chosen. Based on these standards, an ATM over SDH transceiver with add/drop functionality is studied, designed, implemented and verified. This system is described and verified using HDL and, after that, it is synthesized in FPGA devices. The obtained results show that a complex digital system has been developed guaranteeing the specifications, and, on the other hand, the optimization of the human resources and the effort of engineering. This methodology encourages the documentation process while the system is developed, easing the knowledge transfer process.