In this paper, we summarize our development efforts for a top-coatless 193nm immersion positive tone development (PTD) contact hole (C/H) resist with improved litho and defect performances for logic application specifically with an advance node. The ultimate performance goal was to improve the depth of focus (DoF) margin, mask error enhancement factor (MEEF), critical dimension uniformity (CDU), contact edge roughness (CER), and defect performance. Also, the through pitch CD difference was supposed to be comparable to the previous control resist. Effects of polymer and PAG properties have been evaluated for this purpose. The material properties focused in the evaluation study were polymer activation energy (Ea), polymer solubility differentiated by polymerization process types, and diffusion length (DL) and acidity (pKa) of photoacid generator (PAG). Additionally, the impact of post exposure bake (PEB) temperature was investigated for process condition optimization. As a result of this study, a new resist formulation to satisfy all litho and defect performance was developed and production yield was further improved.
As semiconductor process technology moves to smaller dimension, RET (resolution enhancement technology)
becomes more and more important, especially in low k1 processes. From 28nm node to 20nm node, the k1 becomes
smaller with smaller dimension and pitch because exposure tool can provide larger NA (numerical aperture) or smaller
exposure wavelength. SMO (source mask optimization) is a RET solution for low k1 process and provide better
lithographic common process window in single exposure technology.
Base on our studies of aerial image simulation and real wafer experiments on 20nm node, SMO could provide a better
solution for 20nm node with 1.35 NA and 193nm exposure wavelength than the other RET sources (Quasar, C-Quad.,
In the first step, the concerned patterns are important for the optimization because the main purpose of SMO is to
obtain better performance in those. Through SMO iteration, we can find out a better source for our design rule and
concerned patterns (like SRAM, and Small Island patterns). Then, we evaluate whether the simulation results can
provide enough accuracy from real wafer data. Base on this study, we can develop a suitable SMO process for 20nm
In this paper, we will show the optical theory, simulation result and wafer performance of SMO technology.
A new dual bottom antireflectant consisting of an organic antireflectant and a SixOyNz:H (SiON) layer has been designed for metal layers to cover both 45nm and 32nm node logic devices. Simulations have been used to optimize the optical constants of the organic antireflectant. The new antireflectant system has been evaluated on a 1.2NA tool for metal layers. The same organic antireflectant has been successfully applied to via layers at a different thickness. The overall patterning performance including profiles, line width roughness (LWR), overlap depth of focus margin (ODOF) and critical dimension (CD) uniformity before and after etch has been evaluated. The new antireflectant system meets all the patterning requirements for a manufacturable process. An immersion tool at 1.2NA was used to perform lithography tests. Simulation was performed by using ProlithTM software.
As critical dimensions shrink to fit advanced process generation requirements, line width roughness (LWR) has become
more and more important.
As design rules for semiconductor devices shrink, the line width roughness approaches the CD of the line itself. This
leads to poor device performance or even device failure. Thus, an accurate process monitor for LWR is required.
CD-SEM measurements for LWR require a reference to verify the accuracy. TEM has traditionally played this role.
However, its destructive nature, the errors induced by sample preparation, the limited data output and long turnaround
time make routine TEM measurement undesirable.
CD-AFM is a non-destructive technique that is able to generate highly accurate three-dimensional profiles of a sample
surface over tens of microns in the X and Y directions with sub-nanometer resolution.
In this paper we present results that show strong correlation between CD-SEM, TEM and inline CD-AFM based on
measurements of an OPC grating. Based on these results, CD-AFM has successfully replaced TEM as the reference
tool of choice for the R&D stage of a 45nm generation process.
To improve this situation, we have successfully adopted in-line X3D AFM to replace FA TEM as the verification tool in
the R&D stage of a 45nm generation process.
Focus exposure matrix (FEM) using contact mask is applied to two 65-nm production wafers. One wafer is dropped at after etch inspection (AEI) while another one is stopped after tungsten chemical mechanical polishing (WCMP). Gray level value (GLV) and critical dimension (CD) are measured using eProfile(R) at different hole patterns, such as dense, isolate, and static random access memory (SRAM) array of the contact AEI wafer. All results show very reasonable CD variation trends in focus exposure PWQ chart. Defect inspections using eScan(R)300 is performed on WCMP wafer at SRAM array area. The major defects detected are missing, bridging and dark voltage contrast (DVC) which is caused by open or partial open of the contact hole. We found that open defect is mainly sensitive to exposure energy. The higher the exposure energy, the fewer the DVC defects. The GLV map of oval tungsten plug (W-plug) correlates with GLV map of oval contact and DVC defect map very well.
Planarization of gap-filling materials for low-k dual damascene processes is getting more and more important due to the photoresist process window shrinking as the pitch and critical dimensions shrink. Defects, especially pattern collapses, will become a serious problem if there is no global planarization for low-k dual damascene processes. IC manufacturers and materials vendors have proposed several ways to improve the global planarization of gap filling, such as using materials with different viscosities, fine tuning gap-filling material coating recipes, and even using optical or chemical treatments to obtain global planarization. The effect of the different conformalities of the first and second coating materials on coating performance will be discussed.
Two fundamentally different approaches for chemical ArF resist shrinkage are evaluated and integrated into process flows for 90 nm technology node. The chemical shrink and the corresponding gain in process window is studied in detail for different resist types with respect to CD uniformity through pitch, linearity and resist profiles. For both, SAFIER and RELACS material, the sensitivity of the shrink process with respect to the baking temperature is characterized by a temperature matrix to check process stability, and optimized conditions are found offering an acceptable amount of
shrinkage at contact and trench levels. For the SAFIER material, thermal flow contributes to the chemical shrink which is a function of the photoresist chemistry and its hydrodynamic properties depending on the resists’ glass transition temperature (Tg) and the baking temperature: at baking temperatures close to Tg, a proximity and pattern dependent shrink is observed. For a given resist, line-space patterns and contact holes shrink differently, and their resist profiles are affected significantly. Additionally, the chemical shrinkage depends on the size of contact holes and resist profile prior to the application of the SAFIER process. At baking temperatures below Tg some resists exhibit no shrink at all. The
RELACS technique offers a constant shrink for contacts at various pitches and sizes. This shrink can be moderately adjusted and controlled by varying the mixing bake temperature which is generally and preferably below the glass transistion temperature of the resist, therefore no resist profile degradation is observed. A manufacturable process with a shrink of 20nm using RELACS at the contact layer is demonstrated. Utilizing an increased reticle bias in combination
with an increased CD target prior to the chemical shrink, the common lithography process window at contact layer was increased by 0.15um. The results also indicate a possibility for an extension of the shrink to greater than 50nm for more advanced processes.