Standard cell library is the basic for building blocks and SoC (system on chip). And design in current standard cell library always meets the most critical design rule, leading to tight lithography process window and hotspots easily. Besides, passing design rule check (DRC) cannot fully guarantee manufacturability. Lithography simulation check is an essential check item before tape out. It is significant to qualify the standard cell library at the most possible early stage in order to avoid design rework during the tape-out stage. For 14nm technology and below, hotspots appear both inside cell, abut regions of standard cells and pins for routing. Therefore, our paper puts forward a fast DFM-driven standard cell qualification approach to detect the hotspots inside cell and the potential defects from special kinds of pins and abutting standard cells. It can discover problems early and set constraints for placement and routing as early as possible for a fast product yield ramp-up.
Mask three-dimensional effect (M3D) and flare are the critical issues for lithography in advanced technology nodes, especially for the extreme ultraviolet lithography (EUVL). The M3D effect leads to a shrinkage of critical dimension (CD) and the flare causes the unwanted background exposure. To evaluate impact of these two effects on EUVL performances, the process windows (PWs) of various test patterns under nominal condition are firstly simulated. And then an optimal source is selected by comparing PW values. At last, M3D is introduced by considering absorber thickness, and the flare is introduced by adding a constant distribution across the exposure field. All simulations are implemented by employing SLitho, a commercial software from Synopsys. The test patterns in simulations include line space, tip2tip and tip2line patterns, and the gaps of tip2tip and tip2line are 40, 45 and 50nm. The results of simulation show that mask topography will reduce the DOFs of test patterns, and constant flare has almost no effect on the DOFs of many test patterns.
Mask defectivity is a critical challenge to the high-volume production of extreme ultraviolet lithography (EUVL). In a similar way to the optical proximity correction (OPC), mask absorber pattern optimization could weaken the impact of defect on lithography. In order to compensate the amplitude and phase impact caused by the defects on the EUV mask blank, an advanced evolution strategy based on genetic algorithm (GA) combining with manufacturing rule check (MRC) is proposed to optimize the mask pattern. The influences of various defects on lithography are firstly summarized from mass simulation results, as well a novel method based on GA is proposed to compensate the negative impact by defects. Finally, the advantages of the proposed method in convergence efficiency and robustness are validated through comparing with differential evolution (DE) and original GA with simulations on contact patterns and logic patterns with the lithography simulator Sentaurus Lithography (Slitho).
It is of tremendous impact with multilayer defects, which are caused by particles, substrate pits or scratches, in EUV lithography for the high volume manufacturing. Multilayer defects suppress the productivity and utilization rate of the mask blank. In this paper, we did a thorough investigation by conducting imaging simulations on dense and semi-dense patterns including lines and contact holes. The impact of isolated multilayer defects on the imaging of 22nm half-pitch dense line/contact and 33nm half-pitch semi-dense line has been studied, and the CD errors are calculated. The CD error, caused by the planar defect which is smoothed out during the multilayer deposition process, is found to be within ±10% of target values. This CD error can be compensated by adjusting the exposure dose or local pattern size. In contrast, the non-planar defect, which is not being smoothed in the multilayer surfaces, would lead to severe damages to the lithography performance.
Background: As semiconductor technologies continue to shrink, the growth in the number of process variables and combined effects tighten the overall process window, which leads to a more serious yield loss. Yield cannot be totally guaranteed by design rule check and verifications of optical proximity correction, due to complex process variations. The joint effects from unreasonable designs and unstable control of critical dimensions and overlay mainly contribute to the formation of bridging defects in critical interconnect layers. Aim: Our paper puts forward a model to detect the potential bridging region and predicts the corresponding failure probability under a litho-etch-litho-etch process. Approach: The proposed model is based on input error sources from variations of lithography and etch processes. In this scheme, bridging is expected when the minimum space of simulated postetch contours within a specific range is smaller than a user-defined bridging threshold. Gaussian distribution characteristics of line edge roughness (LER) and overlay are considered in the proposed model. Moreover, the proposed model provides meaningful guidelines for bridging prediction with the use of process variation bands. Results: The experiment results indicate consistency and validity of theoretical derivation of the proposed model. The concrete impacts of LER and overlay on the model have been quantitatively analyzed as well. Conclusions: According to the predicted probabilities, the model can early discover potential bridging defects quantitatively by considering the statistical properties of process variations with very few calculations and can give a ranking of failure severity as a decision foundation for design rule optimization.
Use of lithography exposure and metrology tools in production typically results in worse performance than seen on test wafers. Physical design always starts with rough design rule for a new technology node. To evaluate the influence of the inevitable degraded performance on test wafers, our paper put forward a systematic approach to evaluate whether the ability of current process can support the design. The approach utilizes litho-friendly design (LFD) to find the yield killers and conducts pattern classification with pattern matching. Process window discovery (PWD) is used to collect the statistical data to confirm whether the yield killers in LFD simulation will meet the systematic fail on wafer. It is necessary to do mask optimization (MO), source mask optimization (SMO) and design rule optimization (DRO) for the real yield killers. Moreover, design of advanced node may include the patterns inside forbidden pitch range. We do the design rule exploration for metal 2 layer of 14nm technology node and discuss the corresponding solutions for width sensitive zone as well.