As a narrow bandgap semiconductor, the preparation of surface passivation layers on HgCdTe film epilayers is essential in the process of device fabrication. Most new infrared detectors use the mesa structure. A stable and reproducible passivation technology which meets the surface uniform cover of the high aspect ratio mesa is particularly important. Atomic layer deposition (ALD) is a new type of accurate surface thin film preparation technique, which has several characteristics such as depositing large-area uniform films, making the film thickness control at nanometer level feasible, and lower deposition temperature. ALD-ZnS film is prepared on the HgCdTe IRFPAs chip at 65°. I-V and R-V curves are similar to that of IRFPAs with CdTe thermal passivation. This shows that ALD ZnS film has a good potential application in the passivation of high aspect ratio mesa-array HgCdTe devices.
Etching at cryogenic temperature can reduced the etch-induced damage in HgCdTe during etch process, which is important to fabricate high performance IRFPAs (Infrared Focal Plane Arrays) detectors. The etch rates of HgCdTe were examined to be similar at different temperatures and the smoothness of the etched surface improves at cryogenic temperature using a standard process, and the etch rates of different CH<sub>4</sub>/Ar/H<sub>2</sub> plasmas at 123K were also investigated. Addition of H<sub>2</sub> increases the roughness of etched sidewall while has little effect on etched bottom surface roughness, and SiO<sub>2</sub> with a contact layer of ZnS functioned well as etch mask during cryoetching under CH<sub>4</sub>/Ar/H<sub>2</sub> plasmas.
This paper reports the development of 2000×256 format SWIR HgCdTe/Si FPA with multiple-choice gain (i.e. multiple-choice charge handling capacity) for hyperspectral detection. The spectral resolution is about 8nm. To meet the demands of variable low flux detection within each spectral band in the short wave infrared range, low dark current, low noise, variable conversion gains and high SNR (Signal to Noise Ratio) of FPA are needed. In this paper, we fabricate 512×512 pixel 30μm pitch SWIR HgCdTe diode array on Si by using a novel stress-release construction of HgCdTe chip on Si. Moreover, we design low noise, variable conversion gain and large dynamic range read-out integrated circuit (ROIC) and hybridized the ROIC on the HgCdTe diode array on Si substrate. There are 8-choice gains which can be selected locally according to the incident flux to meet high SNR detection demand. By high-accuracy splicing 4 512×512 HgCdTe/Si FPA we get mosaic 2000×512 FPA, and characterizations have been carried out and reveal that the array dark current densities on an order of 10<sup>-10</sup>A/cm<sup>2</sup>, quantum efficiency exceeding 70%, and the operability of 99.5% at operating temperature of around 110K. The SNR of this FPA achieved 120 when illuminated under 5×10<sup>4</sup>photons/pixel.
HgCdTe is one of the dominating materials for infrared detection. To pattern this material, our group has proven the feasibility of SiO2 as a hard mask in dry etching process. In recent years, the SiO<sub>2</sub> mask patterned by plasma with an auto-stopping layer of ZnS sandwiched between HgCdTe and SiO<sub>2</sub> has been developed by our group. In this article, we will report the optimization of SiO<sub>2</sub> etching on HgCdTe. The etching of SiO<sub>2</sub> is very mature nowadays. Multiple etching recipes with deferent gas mixtures can be used. We utilized a recipe containing Ar and CHF<sub>3</sub>. With strictly controlled photolithography, the high aspect-ratio profile of SiO<sub>2</sub> was firstly achieved on GaAs substrate. However, the same recipe could not work well on MCT because of the low thermal conductivity of HgCdTe and CdTe, resulting in overheated and deteriorated photoresist. By decreasing the temperature, the photoresist maintained its good profile. A starting table temperature around -5°C worked well enough. And a steep profile was achieved as checked by the SEM. Further decreasing of temperature introduced profile with beveled corner. The process window of the temperature is around 10°C. Reproducibility and uniformity were also confirmed for this recipe.
To fabricate various advanced structures with HgCdTe material, the Inductively Coupled Plasma
enhanced Reactive Ion Etching system is indispensable. However, due to low damage threshold and
complicated behaviors of mercury in HgCdTe, the lattice damage and induced electrical conversion is
very common. According to the diffusion model during etching period, the mercury interstitials, however,
may not diffuse deep into the material at cryogenic temperature. In this report, ICP etching of HgCdTe at
cryogenic temperature was implemented. The etching system with cryogenic assembly is provided by
Oxford Instrument. The sample table was cooled down to 123K with liquid nitrogen. The mask of SiO2
with a contact layer of ZnS functioned well at this temperature. The selectivity and etching velocity
maintained the same as reported in the etching of room temperature. Smooth and clean surfaces and
profiles were achieved with an optimized recipe.
A 640×512 readout integrated circuit (ROIC) with 15um pixel pitch for middle-wave infrared focal plane arrays (MWIR FPAs) is designed in this paper. The 15um pixel pitch presents several challenges to the ROIC design, such as achieving the required charge storage capacity to preserve the high SNR and reading or processing the pixel signals correctly to achieve the required frame rate. A novel structure that four neighboring pixels share one integration capacitor is presented as a feasible approach to getting a large charge capacity in the limited pixel area. Meanwhile, the pixel circuit chooses the direct injection (DI) which occupies the small layout area as the input stage for MW and contains two sample and hold modules to further increase the charge capacity. Moreover,the peripheral analog signal chain circuit, which is composed of a PMOS source follower, a column amplifier and the complementary output stage, is designed to transfer the signals from unit cell with less voltage loss,lower power consumption, lower noise and higher linearity. More importantly, in our design, only half chain circuit are required therefore the corresponding power consumption will be reduced greatly. In order to accommodate this design, two kinds of pixel signal readout sequences are compared. By adopting the 0.18um 1P6M mixed signal CMOS process, the circuit architecture can make the effective charge capacity of 13Me- per pixel with 1.38V final output range. The 4×4 circuit layout will be fulfilled as a whole and in this way the effective integration capacitor can be increased. According to the simulation results, this circuit works well under 3.3V power supply and achieves 10MHZ readout rate and less than 0.1% nonlinearity.
Proc. SPIE. 9674, AOPC 2015: Optical and Optoelectronic Sensing and Imaging Technology
KEYWORDS: Readout integrated circuits, Signal to noise ratio, Digital signal processing, Capacitors, Interference (communication), Capacitance, Signal processing, High dynamic range imaging, Analog electronics, Digital electronics
The charge packet readout integrated circuit (ROIC) technology for the IRFPAs is introduced, which can realize that every pixel achieves a very high capacity of the electrons storage, and it also improves the performance of the SNR and reduces the saturation possibility of the pixels. The ROIC for the LWIR requires ability that obtaining high capacity for storing electrons. For the conventional ROIC, the maximum charge capacity is determined by the integration capacitance and the operating voltage, it can achieve a high charge capacity through increasing the area of the integration capacitor or raising the operating voltage. And this paper would introduce a digital method of ROIC that can achieve a very high charge capacity. The circuit architecture of this approach includes the following parts, a preamplifier, a comparator, a counter, and memory arrays. And the maximum charge capacity of the pixel is determined by the counter bits. This new method can achieve a high charge capacity more than 1Ge- every pixel and output the digital signal directly, while that of conventional ROIC is less than 50Me- and output the analog signal from the pixel. In this new circuit, the comparator is a important module, as the integration voltage value need compare with threshold voltage through the comparator all the time during the integration period, and we will discuss the influence of the comparator. This work design the circuit with the CSMC 0.35um CMOS technology, and the simulation use the spectre model.
The implementation of an effective readout integrated circuit for 320 x 256 middle-and long-wave infrared focal plane
arrays (MLIR FPAs) imaging system is detailed in this paper. The key purpose of this design is transferring the signals
from dual-color detectors sequentially with effectiveness including lower noise, less voltage loss, lower power
consumption, higher linearity, higher speed etc. A double sharing capacitor (DSC) structure is adopted as a solution to
how to make a trade-off between the areas of capacitors and the main MOSFETs structures. Compared to the traditional
charge transferring, a zero-charge-loss mechanism is applied in this circuit to guarantee a high voltage transferring
efficiency. A three-stage cascaded unit gain amplifiers is used to get a high drive capability and good linearity.
Meanwhile, a simple but effective power management is introduced to the section of arrays and the first output stage to
ensure acceptable power consumption. Moreover, a testing line with adjustable current source is added aside to fulfill the
effective testability. Now, the chip has been fabricated with the 0.35um 2P4M mixed signal technology and finished
basic testing process. According to the testing results, the whole chip presents a sensitive response to illumination and
the output voltage steps are clearly legible at 2.5MHz data transmission rate. As it is expected, this structure achieves
100f/s frame frequency and less than 1% nonlinearity under 5V power supply. However, the output swing reduced to 2V
at room temperature of which the reason should be researched further. The total power consumption reaches 170mW.
Since the technology trend of the third generation IRFPA towards resolution enhancing has steadily progressed,the pixel pitch of IRFPA has been greatly reduced.A 640×512 readout integrated circuit(ROIC) of IRFPA with 15μm pixel pitch is presented in this paper.The 15μm pixel pitch ROIC design will face many challenges.As we all known,the integrating capacitor is a key performance parameter when considering pixel area,charge capacity and dynamic range,so we adopt the effective method of 2 by 2 pixels sharing an integrating capacitor to solve this problem.The input unit cell architecture will contain two paralleled sample and hold parts,which not only allow the FPA to be operated in full frame snapshot mode but also save relatively unit circuit area.Different applications need more matching input unit circuits. Because the dimension of 2×2 pixels is 30μm×30μm, an input stage based on direct injection (DI) which has medium injection ratio and small layout area is proved to be suitable for middle wave (MW) while BDI with three-transistor cascode amplifier for long wave(LW). By adopting the 0.35μm 2P4M mixed signal process, the circuit architecture can make the effective charge capacity of 7.8Me<sup>-</sup> per pixel with 2.2V output range for MW and 7.3 Me<sup>-</sup> per pixel with 2.6V output range for LW. According to the simulation results, this circuit works well under 5V power supply and achieves less than 0.1% nonlinearity.
The high-speed and high dynamic range readout circuits can realize a good performance that achieving intra-scene wide dynamic range，and the readout circuits could get more details of a target view that include very dark and very bright signal. A new architecture of readout circuits with high speed and high dynamic range is introduced. In order to achieve high dynamic range, we use a special architecture of readout circuits. The circuits allow the very high signal to input, and output the signal without damaging. The input stage use a CTIA architecture in the circuits, and connect a feedback circuit and a S/H circuit in the output of CTIA. The architecture of the feedback is a circuit to control the reset switch of CTIA, when a strong signal inputing, the feedback circuit judge the signal of output, if the signal over the reference signal that have been set, the feedback circuit output a reset signal, the output of CTIA is reset to the initial state. A counter records the reset signal, and get the total times of reset. At the last stage of integration period，the S/H circuit samples the signal and a integration period is over. As the circuits could realize multiple reset, the signal would never reach saturation state, and it can achieve a very high range in the output. We use the GLOBALFOUNDRIES 0.35μm technology and simulate the designed circuits with Cadence IC, and test the functions, then analyze the performance of the circuits from the results.
In this paper, a high performance readout integrated circuit (ROIC) designed for long wave infrared (LWIR) detectors is introduced, which has high dynamic range (HDR). To accommodate the wide scene dynamic range requirement, special circuit architecture is used to the input unit cell. A capacitive feedback transimpedance amplifier (CTIA) as input circuit is used to provide high injection efficiency, low input resistance, good linearity, precise voltage bias. Because of the restriction of the layout area, four unit cells will share an integration capacitor and each unit cell has a correlated double sampling (CDS) circuit, which allows the infrared focal plane arrays (IRFPA) to be operated in full frame snapshot mode and provides the maximum integration time available. The charge transfer circuit is used and we don't need to consider the drive ability of the unit cell. The simulation results confirm that the ROIC provides over a factor of 70dB dynamic range with the 5.0v power supply.
In this work, a novel junction profile measurement method is proposed. A serial of junctions were fabricated by B+ implantation. Then a beveled bar which was about 10mm long and several micrometers deep was formed by carefully controlled wet-etching. The remaining depth of n region changes from the full depth that is about 5.3mm after ion implantation to zero depending on its lateral position and the slope of the etching bar. Voltage-current and Laser Beam Induced Current (LBIC) measurements were applied to determine the HgCdTe junction edge. The LBIC signal orrectification characteristic indicates the existence of a PN junction. The junction depth is extracted from the position where the PN junction disappears and the slope of the etching bar. The junction depth of intrinsic doped HgCdTe was measured, which is about 2.4μm. A significant 0.4mm thick N-region was observed. Moreover, junction depths of samples annealed for different time were also investigated. By this method, it’s possible to measure the three dimensional profile of a planar PN junction.
The nBn structure with an electron barrier sandwiched by n-type cap and absorber layers was predicted to suppress the Shockley-Read-Hall (SRH) generation-recombination processes and surface leakage. The MCT nBn structure has been studied by several groups to implement high operating temperature (HOT) device. In this report, the numerical analysis of the Hg<sub>1-x</sub>Cd<sub>x</sub>Te nBn device in LWIR region (<i>x</i>=0.225) is performed utilizing Crosslight APSYS. The detector performance characterized by dark current, photo-current and detectivity is optimized by adjusting structural parameters such as Cd component and doping of each layer under various biases. Among the parameters, the trade-off between ΔEc and ΔEv is most intensively affected by Cd component of the barrier which was modified carefully and accomplished firstly. Furthermore, the effect of the trap density and trap energy level on the device performance is also investigated especially according to the processing techniques. At 110K, the optimized detectivity of the LWIR MCT nBn device reaches 7.5×10<sup>10</sup> cmHz<sup>1/2</sup>/W in this report, comparable with that of the DLPH device (7.6×10<sup>10</sup> cmHz<sup>1/2</sup>/W). The novel nBn HgCdTe structure is potentially valuable in LWIR region since the controllable p-doping issue is circumvented and passivation process is simplified.
An innovative heterojunction photodiode structure in HgCdTe-on-Si long-wavelength (LW) infrared focal plane array (IRFPA) detector is investigated in this paper. The quantum efficiency and the photoresponse of devices have been numerically simulated, using Crosslight Technology Computer Aided Design (TCAD) software. Simulation results indicate that in contrast to the p<sup>+</sup>-on-n homojunction photodiode, the heterojunction photodiode effectively suppresses the
crosstalk between adjacent pixels and interface recombination between HgCdTe active region and
buffer layer on Si substrate. And in the range of the LW-band, the quantum efficiency of the heterojunction photodiode increases by 35.5%. Furthermore, the heterojunction photodiode acquires the narrow-band response spectrum desired in the application of the LW IRFPA detectors
as the p<sup>+</sup>-on-n homojunction photodiode with the optical filter. Finally, the smaller bulk resistance of its heavily doped N-type layer ensures the uniformity of the pixel series resistance in the large format IRFPAs.
This paper describes the simulation results of a high performance readout integrated circuit (ROIC) designed for long wave infrared (LWIR) detectors, which has high dynamic range (HDR). A special architecture is used to the input unit cell to accommodate the wide scene dynamic range requirement, thus providing over a factor of 70dB dynamic range. A capacitive feedback transimpedance amplifier (CTIA) provides a low noise detector interface circuit capable of operating at low input currents and a folded cascade amplifier with a gain of 73dB is designed. A 6.4pF integration capacitor is used for supporting a wide scene dynamic range, which can store 80Me. Because of the restriction of the layout area, four unit cells will share an integration capacitor. A sample and hold capacitor is also part of the input unit cell architecture, which allows the infrared focal plane arrays (IRFPA) to be operated in full frame snapshot mode and provides the maximum integration time available. The integration time is electronically controlled by an external clock pulse. The simulation results show that the circuit works well under 5V power supply and the nonlinearity is calculated less than 0.1%. The total power dissipation is less than 150mW.
HgCdTe electron injection avalanche photodiodes (e-APDs) work at linear mode. A weak optical current signal is amplified orders of magnitude due to the internal avalanche mechanism and it has been demonstrated to be one of the most promising methods to focal-plane arrays (FPAs) for low-flux like hyper-spectral imaging and high-speed applications such as active imaging. This paper presents the design of a column-shared ADC for cooled e-APDs FPA. Designing a digital FPA requires fulfilling very stringent requirements in terms of power consumption, silicon area and speed. Among the various ADC architectures sigma-delta conversion is a promising solution for high-performance and medium size FPA such as 128×128. The performance of Sigma-delta ADC rather relies on the modulator structure which set over-sampling and noise shaping characteristics than on critical analog circuits. This makes them quite robust and flexible. A multistage noise shaping (MASH) 2-1 single bit architecture sigma-delta conversion with switched-capacitor circuits is designed for column-shared ADC, which is implanted in the GLOBALFOUNDRIES 0.35um CMOS process with 4-poly and 4-metal on the basis of a 100um pixel pitch. It operates under 3.3V supply and the output range of the quantizer is 2V. A quantization noise subtraction circuit in modulator is designed to subtract the quantization noise of first-stage modulator. The quantization noise of the modulator is shaped by a high-pass filter. The silicon area and power consumption are mainly determined by the decimation low pass filter. A cascaded integrator-comb (CIC) filter is designed as the digital decimator filter. CIC filter requires no multipliers and use limited storage thereby leading to more economical hardware implementation. The register word length of the filter in each stage is carefully dimensioned in order to minimize the required hardware. Furthermore, the digital filters operate with a reduced supply voltage to 1.5V. Simulation results show that the modulator achieves the resolution higher than 12bits and 2.4mW power consumption per ADC at 7.7k Samples/s rate.
This paper presents a low power and small area analog-digital converter (ADC) for infrared focal plane arrays (IRFPA) readout integrated circuit (ROIC). Successive approximation register (SAR) ADC architecture is used in this IRFPA readout integrated circuit. Each column of the IRFPA shares one SAR ADC. The most important part is the three-level DAC. Compared to the previous design, this three-level DAC needs smaller area, has lower power, and more suitable for IRFPA ROIC. In this DAC, its most significant bit (MSB) sub-DAC uses charge scaling, while the least significant bit (LSB) sub-DAC uses voltage scaling. Where the MSB sub-DAC consists of a four-bit charge scaling DAC and a five-bit sub-charge scaling DAC. We need to put a scaling capacitor Cs between these two sub-DACs. Because of the small area, we have more design methods to make the ADC has a symmetrical structure and has higher accuracy. The ADC also needs a high resolution comparator. In this design the comparator uses three-stage operational amplifier structure to have a 77dB differential gain. As the IR focal plane readout circuit signal is stepped DC signal, the circuit design time without adding the sample and hold circuit, so we can use a DC signal instead of infrared focal plane readout circuit output analog signals to be simulated. The simulation result shows that the resolution of the ADC is 12 bit.
An improved CMOS readout integrated circuit (ROIC) for N-on-P very long wavelength (VLWIR) detectors is designed, which has the ability to operate with a simple background suppression. It increases the integration time and the signal-to-noise ratio (SNR) of image data. A buffered gate modulation input (BGMI) cell as input circuit provides a low input resistance, high injection efficiency, and precise biasing voltage to the photodiode. By theoretically analyzing the characteristic parameters of MOS device at low temperature, a high gain’s feedback amplifier is devised which using a differential stage to provide the inverting gain to improve linearity and to provide tight control of the detector bias. The final chip is fabricated with HHNEC 0.35um 1P4M process technology. The measurement results of the fabricated readout chip under 50K have successfully verified both readout function and performance improvement. With the 5.0V power supply, ROIC provides the output dynamic range over 2.5V. At the same time, the total power dissipation is less than 200mW, and the maximum readout speed is more than 2.5MHz.
This paper presents a real-time processing system designed for infrared FPA. The real-time processing is a key technology in the infrared image processing system<sup></sup>. In this paper, the pre-processing and segmentation approaches are combined in order to achieve a good result from infrared images which have large noise, complex background and ambiguous target<sup></sup>. This design is a real-time IR image processing system based on Xilinx's VIRTEX-5, fully using of VIRTEX-5 FPGA’s high performing, the FPGA embedded Xilinx's MicroBlaze processor core, and high-performance pre-processing function modules. Data signals processed by FPA can be collected to carry out filtering calculation, and the LCD displays the image, user can control the system by touching screen real-time.
Time of flight laser range finding, deep space communications and scanning video imaging are three applications requiring very low noise optical receivers to achieve detection of fast and weak optical signal. HgCdTe electrons initiated avalanche photodiodes (e-APDs) in linear multiplication mode is the detector of choice thanks to its high quantum efficiency, high gain at low bias, high bandwidth and low noise factor. In this project, a readout integrated circuit of hybrid e-APD focal plane array (FPA) with 100um pitch for 3D-LADAR was designed for gated optical receiver. The ROIC works at 77K, including unit cell circuit, column-level circuit, timing control, bias circuit and output driver. The unit cell circuit is a key component, which consists of preamplifier, correlated double Sampling (CDS), bias circuit and timing control module. Specially, the preamplifier used the capacitor feedback transimpedance amplifier (CTIA) structure which has two capacitors to offer switchable capacitance for passive/active dual mode imaging. The main circuit of column-level circuit is a precision Multiply-by-Two circuit which is implemented by switched-capacitor circuit. Switched-capacitor circuit is quite suitable for the signal processing of readout integrated circuit (ROIC) due to the working characteristics. The output driver uses a simply unity-gain buffer. Because the signal is amplified in column-level circuit, the amplifier in unity-gain buffer uses a rail-rail amplifier. In active imaging mode, the integration time is 80ns. Integrating current from 200nA to 4uA, this circuit shows the nonlinearity is less than 1%. In passive imaging mode, the integration time is 150ns. Integrating current from 1nA to 20nA shows the nonlinearity less than 1%.
Ultra-low light imaging and passive/active dual mode imaging require very low noise optical receivers to achieve
detection of fast and weak optical signal. HgCdTe electrons initiated avalanche photodiodes (e-APDs) in linear
multiplication mode is the detector of choice thanks to its high quantum efficiency, high gain at low bias, high bandwidth
and low noise factor. In my work, a passive/active dual mode readout integrated circuit (ROIC) of e-APD focal plane
array (FPA) is designed. Unit cell circuit architecture of ROIC includes a capacitance feedback transimpedance amplifier
(CTIA) as preamplifier of ROIC, a high voltage protection module, a comparator, a Sample-Hold circuit module, and
output driver stage. There is a protection module in every unit cell circuit which can avoid ROIC to be damaged from
avalanche breakdown of some diodes of detector. Conventional 5V CMOS process is applied to implement the high
voltage protection with the small area rather than Laterally Diffused Metal Oxide Semiconductor (LDMOS) in high
voltage BCD process in the limited 100um×100um pitch area. In CTIA module, three integration capacitances are
included in the CTIA module, two of them are switchable to provide different well capacity and noise. Constraints such
as pixel area, stability and power lead us design toward a simple one-stage cascade operational transconductance
amplifier (OTA) as pre-amplifier. High voltage protection module can protect ROIC to be damaged because of
breakdown of some avalanche diodes.
Design of readout-integrated circuit(ROIC) with high frequency and low signal for 512×256 short wavelength(SW) inferred-focal-plane-arrays(IRFPAs) is presented. The ROIC with high performance in frame rate can integrate and read out the low signal. An analog signal chain, which contains CTIA, CDS module, amplifier of charge and complementary output stage, can satisfy the high frequency and low signal application. A reliable digital control structure of IRFPA ROIC is presented, with which the integral voltage of arbitrary contiguous or noncontiguous lines, rather than regular lines, can be selected to readout. The simulation and verification are completed both before and after completing the layout. The circuit’s structure and operation principle are analyzed under the environment of mix-signal, and the result shows that the output dynamic range is over 2.5V, the charge capacity is more than 1Me-, the frame rate is 250Hz, the linearity within useful dynamic range is above 99.9 percent.
Infrared focal plane HgCdTe device is used in the environment of complicated astrospace radiation. To achieve the instrument’s actual service life, the anti-radiation ability is needed to study in our research. The irradiation-induced invalidation mechanism of semiconductor materials is introduced in this paper, and the screening experiments' total radiation dose of American Military Standard is also investigated in our study. Through the simulation of astrospace radiation effect by <i>γ</i> -irradiation, the experimental procedures are proved to be rational by the analysis of the experimental data. With the domestic conditions, radiation screening procedures which meets the practical need is suggested.
HgCdTe electrons initiated avalanche photodiodes (e-APDs) in linear multiplication mode can be used for high speed applications such as active imaging. A readout integrated circuit of e-APD FPA is designed for dual mode passive/active imaging system. Unit cell circuit architecture of ROIC includes a high voltage protection module, a Sample-Hold circuit module, a comparator, output driver stage and a integrator module which includes a amplifier and three capacitors. Generally, APD FPA works at reversed bias such as 5V-15V in active imaging mode, and pixels’ dark currents increase exponentially as the reverse-bias voltage is increased. Some cells of ROIC may be short to high voltage because of avalanche breakdown of diodes. If there is no protection circuit, the whole ROIC would be burnt out. Thus a protection circuit module introduced in every ROIC cell circuit is necessary to make sure the rest units of ROIC can still work. Conventional 5V CMOS process is applied to implement the high voltage protection with the small area other than LDMOS in high voltage BCD process in the limited 100μm×100μm pitch area. In integrator module, three integration capacitors are included in the ROIC to provide switchable well capacity. One of them can be shared in two modes in order to save area. Constraints such as pixel area and power lead us design toward a simple one-stage cascade operational transconductance amplifier (OTA) as pre-amplifier which can avoid potential instability caused by inaccuracy of MOSFET Model at 77K.
A readout integrated circuit (ROIC) for 320× 256 middle-wave and long-wave infrared focal plane arrays, is studied in this paper. This circuit operates in integrating-while-reading (IWR) mode with the frame rate higher than 100fps. A novel DI structure is used for signal acquisition of middle wave while BDI structure for long wave. It is common that trade-offs always exist between chip area and performances in integrated circuits design. In order to get high injection efficiency for BDI structure with small area, a four-transistor amplifier with a gain of 82dB is designed. The charge capacity of ROIC is also a key performance parameter when considering the noise and the large middle-wave and longwave photocurrent (up to 5nA and 100nA, respectively). A structure named double sharing capacitors (DSC) presented in this paper will be an effective solution to getting a large capacity in the limited 50 μm x 50 μm pitch area. DSC means that each integrating capacitor has two kinds of shares. One is between the integrating capacitor and another integrating capacitor which is in the adjacent pixel, and the other is between the integrating capacitor and the holding capacitor in the same pixel. By adopting the 0.35μm 2P4M mixed signal process, the DSC architecture can make the total effective charge capacity as high as 70Me- per pixel with 3V output range. According to the simulation results, this circuit works well under 5V power supply and achieves 2.5MHz data transmission rate, less than 0.1% nonlinearity. Its total power consumption is less than 110mW.
High frequency readout-integrated circuit(ROIC) of 512×256 staring short wavelength(SW) infrared focal plane arrays(IRFPAs), focusing on high-frame rate output and noise suppression is implemented in this paper. The design of ROIC mentioned in it takes the previous version into account. The complete analog signal chain contains a novel input stage of capacitor feedback transimpedance amplifier(CTIA) preamplifier, a CDS (correlated double sampling) module, an amplifier of charge and complementary output stage. This ROIC is a full-custom flow integrated circuit design. The parasitic parameters are extracted once the layout is finished. Then the design is improved according to the result of post-layout simulation, which leads to the great improvements of the majority of parameters. The test and simulation results show that the output voltage range is 2.8V, the frame rate is 250Hz and the linearity within useful voltage range is above 99.1 percent, even when the temperature is 77K.
This paper presents a low power ADC for the 512*512 infrared focal plane arrays (IRFPA) readout integrated circuit(ROIC). The major structure, the working mode and the simulation result of the readout integrated circuit are shown in this paper. The power supply voltage of 0.35μm standard CMOS process is 3.3V in this design, and then the output range of the Direct Injection (DI) input circuit is reached 2V. Successive-approximation-register (SAR) ADC architecture is used in this readout integrated circuit. And each ADC is shared by one column of the IRFPA. This SAR ADC is made up of a 13-bit digital-analog converter (DAC), a high resolution comparator, and a digital control circuit. The most important part is the voltage-scaling and charge-scaling charge redistribution DAC. In this DAC, charge scaling with a capacitor ladder to determine the least significant bits is combined with voltage scaling with a resister ladder to determine the most significant bits. The comparator uses three-stage operational amplifier structure to get a 77dB differential gain. The Common-Mode input rang of the comparator is 1V to 3V, and minimum resolvable voltage difference is 0.3mV. This SAR ADC has some advantages, especially in low power and high speed. The simulation result shows that the resolution of the ADC is 12 bit and the conversion time of the ADC is 6.5μs, while the power of each ADC is as low as 300μW. Finally, this SAR ADC can satisfy the request of 512*512 IRFPAs ROIC with a 100Hz frame rate.
N<sub>2</sub> atmosphere annealing process to recover ICP etching induced damage on p type mercury vacancy HgCdTe film has been exploited in this paper. ICP etching and N<sub>2</sub> atmosphere annealing processes were carried out on a series of Hgvacancy-doping p-type HgCdTe samples. The carrier transport and lifetime properties of these samples were characterized by Hall measurement and microwave reflectance method respectively. P-to-n electrical damage of the surface HgCdTe film induced by the ICP etching process was deduced from the polarity inversion of Hall coefficient. The carrier transport and lifetime properties were similar to those of the non-etched samples, indicating that the surface HgCdTe electrical damage was recovered partially by annealing at 210°C for 2 hours. I-V and R-V characteristics curves of photodiodes fabricated on the etched and N<sub>2</sub> atmosphere annealing processed MCT samples were also comparable to those of photodiodes on the non-etched MCT samples in the following experiments. These results show that N<sub>2</sub> atmosphere annealing process is a readily available and promising recovering technique for HgCdTe ICP etching induced damage.
A novel mask technique, combining high selectivity silicon dioxide patterns over high aspect-ratio
photoresist (PR) patterns has been exploited to perform mesa etching for device delineation and electrical
isolation of HgCdTe third-generation infrared focal plane arrays (IRFPAs). High-density silicon dioxide film
covering high aspect-ratio PR patterns was deposited at the temperature of 80°C and silicon dioxide film
patterns over high aspect-ratio PR patterns of HgCdTe etching samples was developed by standard
photolithography and wet chemical etch. Scanning electron microscopy (SEM) shows that the surfaces of
inductively coupled plasma (ICP) etched samples are quite clean and smooth. The etching selectivity between
the novel mask and HgCdTe of the samples is increased to above 32: 1 while the side-wall impact of etching
plasma is suppressed by the high aspect ratio patterns. These results show that the combined patterning of
silicon dioxide film and thick PR film is a readily available and promising masking technique for HgCdTe
In this paper, a new design of readout integrated circuit application in short wave infrared is introduced.
An amplifier of one transistor is employed in the CTIA to reduce the area of the unit cell. The output
unit cell achieved CDS (correlated double sampling) and SH (sample and hold) is designed for public
use of a whole line, and is outside the array. A new digital control structure of IRFPA ROIC is
presented, with which the integral voltage of arbitrary contiguous or noncontiguous lines, rather than
regular lines, can be selected to readout. The structure of the circuitry and the operation principle are
analyzed, showing that the output dynamic range is over 2.5V, the cell capacity is more than 0.5Me<sup>-</sup> the
frame rate is 250Hz, and the linearity within working dynamic range is above 99.9 percent. This design
is going to be fabricated through Chartered 0.35um double-poly-four-metal (DPFM) process technique,
and the pixel occupies a 30um by 30um area.
In our study, we designed a 512×512 readout integrated circuit (ROIC) for N-on-P short wave infrared
(SWIR) detectors, which has the ability to operate with two capacitors for different input current levels
from very low background applications to daytime high illumination conditions. A buffered direct
injection (BDI) readout cell as input circuit provides a low input resistance, high injection efficiency,
and precise biasing voltage to the photodiode at low input currents. In order to reduce the noise of the
BDI readout cell, a high-performance single stage amplifier is devised, the gain of which reaches as
high as 50dB. The input MOSFET of the amplifier operates at sub-threshold region to keep the
photodiode at precise reverse bias and steady injection efficiency. At the same time, with the input
MOSFET at sub-threshold region, the current is smaller than at saturation region, and the power
dissipation is reduced to a low level. A sample and hold circuit is also part of the input unit cell
architecture, which allows the infrared focal plane array (IRFPA) to be operated in full frame snapshot
mode and rolling mode. To prevent the excess of total current of the ROIC, the reset time of every row
has a lag of one period compared to the previous row. The simulation results confirm these advantages.
With the 5.0V power supply, ROIC provides the output dynamic range over 2.5V, the well capacity
more than 1×10<sup>6</sup>e-, and the total power dissipation less than 120mW. The final chip is fabricated with
HHNEC 0.35um 1P4M process technology, and the pixel occupies a 30um×30um area. The Testing
results are coincide with the simulations of the circuit. With the detecting current varies from 30pA to
1nA, the linearity of BDI is 99%, and it can be operated at the temperatures below 77K.
With the development of the infrared focal plane detectors, the internal noises in the infrared focal
plane arrays (IRFPAs) CMOS readout integrated circuit gradually became an important factor of the
development of the IRFPAs. The internal noises in IRFPAs CMOS readout integrated circuit are
researched in this work. Part of the motivation for this work is to analyze the mechanism and influence
of the internal noises in readout integrated circuit. And according to the signal transporting process,
many kinds of internal noises are analyzed. According to the results of theory analysis, it is shown that
1/f noise, KTC noise and pulse switch noise have greater amplitude in frequency domain. These noises
have seriously affected the performance of output signal. Also this work has frequency test on the
signals of a readout integrated circuit chip which is using DI readout mode. After analyzing the
frequency test results, it is shown that 1/f noises and pulse switch noises are the main components of
the internal noises in IRFPAS CMOS readout integrated circuit and they are the noises which give a
major impact to the output signal. In accordance with the type of noise, some design methods for noise
suppression are put forward. And after the simulation of these methods with EDA software, the results
show that noises have been reduced. The results of this work gave the referenced gist for improving the
noise suppression design of IRFPAs CMOS readout integrated circuit.
Hydrogen-based dry plasmas, generated in inductively coupled plasma reactors have been demonstrated to be very
effective in fabricating high fill-factor mesa of Hg<sub>1-x</sub>Cd <sub>x</sub>Te multi-layer hetero-structure material for infrared focal plane
array applications. To obtain reasonable dry etching process for Hg <sub>1-x</sub>Cd<sub> x</sub>Te, it is essential to investigate the physical,
chemical, and electrical characteristics of the surface. This paper explores the effect of varying the plasma process
parameters on the surface of Hg <sub>1-x</sub>Cd<sub> x</sub>Te. The surface chemical analysis was carried out using spot X-ray photoelectron
spectroscopy (XPS), the surface roughness was measured by atomic force microscopy (AFM), and p-to-n type
conversion depth was assessed by a reliable current-voltage test of a designed structure basing on material-chip
technology concept and a convenient technology of cross-section surface potential imaging (SPM). At last, Hg <sub>1-x</sub>Cd<sub> x</sub>Te
etched surfaces with roughness low and mechanical or electrical damage free were achieved.
A novel 256×1 readout integrated circuit (ROIC) with simultaneous integration mode for two-color
(MWIR/LWIR,MWIR/SWIR) n-p-P-P-N HgCdTe infrared detectors is presented in this paper. This ROIC features an
input stage based on current mirror integration (CMI) structure, which separates MW (SW) photocurrent signal from
mixed signals of LW and MW (MW and SW) and each waveband photocurrent signal is capable to be integrated in
uncorrelated-simultaneous mode. A test chip of 256×1 ROIC is designed and fabricated with 0.6μm double poly double
metal mixed signal technology. The chip test results prove right function of the circuit. It shows good performance of
integration of MW and LW signals. The linearity of MW and LW output voltage- input current curve is over 99%. Power
dissipation of the circuit is less than 50 mW. Readout clock frequency is up to 2 MHz.
The high-density inductively coupled plasma etching technique was applied to HgCdTe, while using the RF-powered wafer electrode to provide low plasma energy. By using a CH<sub>4</sub>/H<sub>2</sub>/N<sub>2</sub>/Ar chemistry the HgCdTe etch profiles were studied as a function of mask selectivity, chamber pressure, gas ratio and ICP power. The etch rate was found to decrease as etch depth increasing. The LBIC and I-V measurements were employed to investigate the electrical damage of HgCdTe material caused by plasma bombardment.
Pixel level on-focal-plane analog to digital conversion(ADC) promises many advantages including high performance and low power consumption. In this paper we argue that CMOS technology scaling will make pixel level ADC increasingly popular. Then we introduce four existing techniques for pixel level ADC. The first is an over sampling technique which uses a one bit first order sigma delta modulator for each pixel to directly convert photo charge to bits, consists of an integrator, a one bit DAC and a clocked comparator. The second technique is Nyquist rate multi-channel-bit-serial(MCBS) ADC. The technique uses special successive comparisons to convert the pixel voltage to bits. The third technique bases on a simple and robust pulse frequency modulation(PFM) scheme that can convert the photocurrent of photodetectors to proportional pulse frequency. The fourth is a software-controlled ADC, which utilize a algorithm, takes a desired photocurrent quantization scale to output bits. Each pixel contains a programmable digital processing element which directly controls the behavior of the photo detector with software. These four techniques are analyzed and compared according to their advantages, disadvantages and suitable application area. Finally we mention our current and future works with one of these techniques.
This paper presents the recent progress on the study of device processings at multilayer HgCdTe film for integrated two-color (SWIR/MWIR) n-p-P-P-N detector arrays. The four-layer p-P-P-N heterostructures Hg<sub>1-x</sub>Cd<sub>x</sub>Te film needed to achieve two color detector arrays was grown by molecular beam epitaxy (MBE) on (211)B oriented GaAs substrates. The secondary ion mass spectroscopy (SIMS) data for the HgCdTe film was obtained. The p-type layer on top of a thin P-type potential barrier layer and the SWIR P-on-N homojunction photodiode formed in-situ during MBE growth using indium impurity doping was processed into the MWIR planar photodiode by selective B<sup>+</sup>-implantation. The preliminary 256×1 linear arrays of SWIR/MWIR HgCdTe two-color FPAs detector were then achieved by mesa isolation, side-wall passivation and contact metallization. At 78K, the average R0A values of SWIR and MWIR are 3.852×10<sup>5</sup> Wcm<sup>2</sup> and 3.015×10<sup>2</sup> Wcm<sup>2</sup>, and the average peak detectivities D<sub>λp</sub><sup>*</sup> are 1.57×10<sup>11</sup>cmHz<sup>1/2</sup>/W and 5.63×10<sup>10</sup> cmHz<sup>1/2</sup>/W respectively. The SWIR photodiode cut-off wavelength is 3.04μm and the MWIR photodiode cut-off wavelength is 5.74μm, quite consistent with the initial device design. The SWIR response spectrum of the two-color detector with a distinct fall-off at shorter wavelength regime was discussed especially.
This paper describes some recent results on surface defects, uniformity, dislocation density as well as device applications of MBE growth of HgCdTe at the research center of advanced materials and devices. The features of different surface defects and their origins were studied by using SEM/EDX observations on HgCdTe epilayers with different growth conditions. A variety of surface defects was observed and the formation mechanism was discussed. A good uniformity was observed over 3-in HgCdTe wafers, the Stddev/mean in x and thickness were 1.2%, and 2.7%, respectively. It was found that the dislocation density was sensitive to growth parameters and the composition. The ZnCdTe substrates with 4% mole fraction were found to be suitable for LW HgCdTe, however, for the HgCdTe of shorter wavelengths different Zn composition is required. An average value of EPD of 4.2×10<sup>5</sup>cm<sup>−2</sup> was obtained for LW samples. The MBE grown HgCdTe were incorporated into some preliminary FPA devices.
The recent progress in MBE growth of HgCdTe at the Research Center for Advanced Materials and Devices, and the National Laboratory for Infrared Physics is reported. It is found that the excellent compositional uniformity and reproducibility of HgCdTe can be archived by MBE technique. The results of surface morphology, dislocation density, electrical properties and focal plane array detectors are described in the paper.