Silicon photonics has emerged as an attractive technology for developing low-cost and high-speed optical communication and optical interconnects. We design a test station which enables semi-automatic for optical-optical and electro-optical testing of passive and active device. Advances in automated wafer-level optical test enable statistical photonic device characterization for development, photonic modeling, and manufacturing controls. Meanwhile we study the influence of fiber tilt angle and height on the measurement.
Silicon nitride material is widely used in photonics and other disciplines such as biology, life sciences, data communication, and sensing. These applications benefit from that silicon nitride has a much broader wavelength transparency range, lower propagation loss and lower thermo-optical coefficient compared with silicon material. However, it is very difficult to deposit thick silicon nitride films on large size wafer directly, which introduces a larger tensile stress and may produce cracks. In this paper, a process to fabricate crack-free 400-nm-thick silicon nitride films was discussed, leveraging 200- mm silicon photonics platform, which is compatible with CMOS process. The silicon nitride layer was deposited on the buried oxide layer via low-pressure chemical vapor deposition in two steps, followed by annealing separately, which can effectively overcome the problem of excessive stress in the films. Chemical mechanical polish technique was applied to planarize the silicon nitride layer and the oxide cladding layer. Annealing improves the uniformity and reduces the stress of the silicon nitride films. Using this process, 1-μm-wide strip waveguide was obtained with low propagation losses for the C-band (0.65 dB/cm). Furthermore, the propagation loss of 0.9-μm-wide strip waveguide was measured to be 0.7dB/cm; the insertion loss of 1×2 multi-mode interference was less than 0.3dB and the non-uniformity was smaller than 10%; the insertion loss of crossing was approximately 0.17dB and the crosstalk was lower than -40dB.
With the rapid development of artificial intelligence, the traditional computer architecture can no longer meet the growing computing performance requirements. At the same time, with the chip manufacturing process approaching the physical limit, a single electronic technology cannot adapt the rapid development of artificial intelligence chips, so there is an urgent need for new computing chips. Photonic neural network chip, which combines artificial intelligence, silicon photonic, integrated circuit and other technologies, will get unprecedented opportunities for the development. Silicon based opto-electronic integration is a large-scale integration technology with optical signal as the main information carrier. It can integrate micro-nano-size optical and electrical devices on the silicon substrate, to form a new large-scale integration chip with comprehensive functions. At present, the development of silicon photonic devices is mainly focused on the field of optical communication and data center, while silicon photonic devices for photonic neural networks are still in the initial stage. Starting from the underlying unit devices, silicon-based photonic devices were studied deeply by combining the artificial neural network with the silicon photonic technology in this paper. Based on 200 mm CMOS process, a lot of process modules for photonic neural network were developed. According to the characteristics of photonic neural network architecture and the performance requirements for the basic unit devices, a series of silicon photonic devices, such as waveguides, grating couplers, MMI, thermal modulators, and other unit devices, were designed and developed. These devices provide important basic conditions for the implementation of high performance photonic neural network chips.
In this work, an ultra-compact and high sensitivity ring resonator-based liquid sensor on a CMOS-compatible SOI platform, utilizing a horizontal slot hybrid plasmonic (HP) waveguide consists of the Cu plasmonic layer suspending above the Si channel waveguide as the sensing element, is proposed. Numerical results suggest that the waveguide sensitivity, 𝑆𝑤, of the proposed HP waveguide reaches as high as 0.84 with the propagation loss less than 0.06 dB/μm, showing a similar Sw and a lower propagation loss in comparison to the typical plasmonic waveguide. In addition, with the scenario of SOI photonic platform continuously standardizing with the established CMOS methodologies for taking the advantages of the CMOS technology, the proposed miniaturized liquid sensor employing the Cu plasmonic element indicates the potential for the monolithic electronic-photonic integration. The sensitivity of the proposed liquid sensor with a miniaturized radius of 2 μm is numerically demonstrated as 540.0 nm/RIU, which is approximately four times higher than that of the conventional Si ring resonator with the identical geometry. Meanwhile a larger FOM is also achieved in comparison to other reported HP ring sensors.
IMECAS is developing a silicon photonics process platform based on existing 22nm CMOS platform. Developing this platform requires continuous process optimization and design verification, so the wafer-level test solution presented in this paper plays an extremely important role in process validation and optimization. We design a test station which enables manual and semi-automatic for optical and electro-optical testing of passive and active silicon photonics components and circuits, including waveguides, grating couplers, splitter, photo-detectors, modulators etc. It is compatible with 200mm wafer-level testing and Die-level testing. Meanwhile, it has two coupling ways: horizontal coupling and vertical coupling. The measured repeatability of S-parameters and IV is within 6α.
Silicon photonics uses mature CMOS industry to design, manufacture and package photonic devices. It can break through the limitation of existing electrical technology in terms of cost, power consumption and integration, to meet the needs for future development of communication, data center, LiDAR, biosensor, quantum computing, etc. Although silicon photonics process is based on CMOS technology and facilities, a mature CMOS platform can not be seamlessly transformed into a silicon photonics platform, because there are great differences in device types and graphic characteristics between photonics and electrical integrated circuits. The key challenges and solutions in developing a manufacturable photonic technology were described in this paper. According to the difference of manufacturing process, a series of process modules for silicon photonics were developed on 200-mm CMOS platform, such as silicon deep-etch process for edge-coupling technology. An abundant device library for process design kit was established, including stripe waveguide, rib waveguide, grating coupler, MMI, directional coupling, waveguide crossing, AWG, MZ modulator, and photodetector. Meanwhile, Si3N4 material is also one of the important materials for future development of photonic integration. Through process optimization, the propagation loss of Si3N4 waveguide were approximately 0.2 dB/cm with thickness of 100 nm and 0.6 dB/cm with thickness of 400 nm, respectively. Automated wafer-level optical test was used to enable statistical photonic device characterization for development, photonic modeling, and manufacturing controls.
Silicon photonics is poised to revolutionize many application areas, such as telecommunication, date centers, biosensing, high performance computing, etc. A whole silicon photonics process flow based on 200mm CMOS platform and the performance of photonics devices were described in this paper. A series of optimized process, including photolithography, etching, hydrogen annealing, ion implantation, epitaxial growth, etc., are implemented to fabricate low-loss passive devices and high-speed active devices. The propagation loss is sensitive to sidewall roughness originated from the waveguide-patterning process. Hydrogen annealing is an effective method to reduce the propagation loss of waveguides. Every level of implantation in top silicon layer is performed respectively, including the p++, p+, p, n++, n+ and n doping for the modulators, p++, p+, n++ and n+ implants for Ge photodetector. Epitaxial Ge is considered to be an excellent material for photodetectors. High-quality Ge on silicon is grown via selective epitaxy using SiO2 as growth mask, followed by a CMP process to planarize the top of the selectively grown Ge. In our platform, the propagation loss of waveguide is measured to be 2.5dB/cm, the insertion loss of grating coupler at 1550nm is 4.5dB/facet, the crosstalk of cross waveguide is lower than -30dB, the insertion loss of 8 channels 200GHz AWG is approximately 3.3dB, the 3dB bandwidth of MZ modulator achieves higher than 20GHz, and the Ge photodetector operates at high data rate exceeding 40Gbps.