Advances in pattern-based layout tools enable automatic and rapid capture, tailoring, creation, classification, and comparison/matching (accurate or fuzzy) of large quantities of patterns. Applications of such tools have significantly improved traditional script- or manual- based approaches, and have produced impressive results in production OPC and mask work. In this work, we introduce into NXP mask preparation a flow with pattern-matching-assisted mask data inspection solution, employing Cadence Pattern Analysis (CPA) tool. We also engage in CPA-facilitated creation of pattern libraries to achieve more comprehensive results in more automatic ways than what could be realized with traditional approaches, and utilize these patterns to accelerate OPC tuning, monitoring, and optimization.
As an important resolution enhancement technique (RET), alternating aperture phase shift masks (AAPSM) has been widely adopted in 90 nm technology node and beyond. Mask topographical effect due to the 3D nature of the shifter features is becoming an increasingly important factor in lithography modeling. Rigorous 3D modeling of PSM is very computationally demanding thus impractical for full chip optical proximity correction (OPC). Here we introduce an alternative approach employing boundary layers to effectively approximate the 3D mask effect. We will present the model calibration versus real wafer data using the boundary layers and the corresponding OPC correction flow.
Complementary Phase Shift Mask (c:PSM) has been a key photolithographic technique employed by chip makers, including Motorola, to fabricate 130nm-node devices. Advancing from the 130nm to 90nm technology generation, the c:PSM process needs fundamental improvements in order to meet new challenges such as tighter CD tolerance, smaller pitches, etc. In this paper we describe the challenges and our efforts to develop a c:PSM process for the 90nm technology, with a particular emphasis on the gate layer patterning. The significantly increased pattern density led to our strategy to phase shift not only gates but also some routing lines. As a result, more features are prone to phase conflicts. These phase conflicts have been avoided by enforcing more constrains on design rules, optimizing shifter/trim parameters, improving the coloring methods in the software, and even manually handling special cases. Model-based OPC has been applied to both masks with models rigorously calibrated to resist data. Small budget for CD variation imposes stringent requirements on both model accuracy and algorithm robustness. The double exposure process required by the c:PSM process aggravates the difficulties, by introducing issues such as different process conditions in the two exposures, intensity imbalance, connection between segment movements in the two masks, etc. The models and correction algorithm have been tuned to accommodate these issues. Both rule-based and simulation-based verification have been utilized to check mask manufacturability, susceptibility to defects, and pattern fidelity. In particular, a structural checking mechanism has been built for complexities created by the double exposure process. Significant effects from intensity imbalance have been observed on wafer at small pitches. Work is under way to alleviate the intensity imbalance by using different mask making techniques.
In this paper we introduce the concept and design of a novel phase shift mask technology, Polarized Phase Shift Mask (P:PSM). The P:PSM technology utilizes non-interference between orthogonally polarized light sources to avoid undesired destructive interference seen in conventional two-phase shift mask technology. Hence P:PSM solves the well-known 'phase edge' or 'phase conflict' problem. By obviating the 2nd exposure and 2nd mask in current Complementary Phase Shift Mask (C:PSM) technology, this single mask/single exposure technology offers significant advantages towards photolithography process as well as pattern design. We use examples of typical design and process difficulties associated with the C:PSM technology to illustrate the advantages of the P:PSM technology. We present preliminary aerial image simulation results that support the potential of this new reticle technology for enhanced design flexibility. We also propose possible mask structures and manufacturing methods for building a P:PSM.
Gate patterning has always been held to tight specifications for CD variation compared to other layers. Specifically, the gate layer is more concerned with the total CD variations including Across Chip Linewidth Variation (ACLV), Across Wafer Linewidth Variation (AWLV), CD variation through pitch (Proximity bias), than other layers. Therefore, complementary phase shift (c:PSM) imaging has been introduced at the gate layer under the assumption that it will reduce the total CD variation compared to binary imaging. However, c:PSM data conversion of random logic can introduce additional biases that also impact CD control. These new biases include CD variation as a function of shadow size, reticle-to-reticle overlay error, shifter width, and shifter height (a function of the transistor width and the shifter extension). This paper will show the improvements in ACLV and AWLV using c:PSM. This paper will also look at the increase in the proximity bias for c:PSM compared to binary imaging and show results for implementing a 1-D OPC correction on the phase shift reticle. In addition, this paper will also look at the magnitude of the various additional c:PSM biases mentioned. This paper will discuss the interaction of the different phase shift conversion input parameters for complex random logic and the limitations they impose on how tight we can make the final CD distribution. Finally, since c:PSM allows for selective sizing of CDs over active and over field, a brief discussion will also be given for the CD control of the complementary binary reticle.