The lack of defect-free EUV photomask blanks is one of the multiple challenges in the application of EUV lithography for high volume wafer manufacturing. In EUV photomask manufacturing, shifting the design before writing to avoid patterning over blank defects (pattern shift process) is one of the methods for defect mitigation. A reliable pattern shift process depends upon precise image placement during EUV mask writing. Specifically, accurate determinations of centrality, mean shift distances and residual image placement (IP) errors (3σ) are required and reports describing pattern shift processes1-8 echo this importance of accurate IP during EUV photomask writing. The pattern shift process detailed in this report improves IP accuracy for EUV photomasks aligned on fiducial marks (FM) and increases the budget of potential pattern shifts, while remaining within the mask centrality specification limits. Our process is demonstrated on EUV products where <5 nm 3σ of uncorrected IP error for aligned patterns was achieved.
We quantitatively evaluate Nuflare’s latest resist charging effect correction (CEC) model for advanced photomask
production using e-beam lithography. Functionality of this CEC model includes the simulation of static and timedependent
charging effects together with an improved calibration method. CEC model calibration is performed by
polynomial fitting of image placement distortions induced by various beam scattering effects on a special test design
with writing density variations. CEC model parameters can be fine tuned for different photomask blank materials
facilitating resist charging compensation maps for different product layers. Application of this CEC model into
production yields a significant reduction in photomask image placement (IP), as well as improving photomask overlay
between critical neighbouring layers. The correlations between IP improvement facilitated by this CEC model and single
mask parameters are presented and discussed. The layer design specifics, resist and blank materials, coupled with their
required exposure parameters are observed to be the major influences on CEC model performance.
Strict reticle critical dimension (CD) control is needed to supply ≤ 20nm wafer technology nodes. In front end
lithographic processes for example, precise temperature control in resist baking steps is considered paramount to limiting
reticle CD error sources. Additionally, current density during writing and focus are continuously tracked in 50kV e-beam
pattern generators (PG) in order to provide stable CD performance. Despite these strict controls (and many others),
feedback compensation strategies are increasingly utilized in mask manufacturing to reach < 2nm 3σ CD uniformity
(CDU). Such compensations require stable reticle CD signatures which can be problematic when alternate or backup
process tools are employed. The AMTC has applied principle component analysis (PCA) to resist CD measurements of
50kV test reticles fabricated with chemically amplified resists (CAR) in order to quantify the resist CDU capabilities of
front and backup lithographic process tools. PCA results elucidate significant resist CDU differences between similar
lithographic process tools that are considered well matched via CDU 3σ comparisons.
The utility of PCA relies on the statistical analysis of large data sets however, reticle CD sampling is typically sparse, on
the 10-2 m or centimeter (cm) scale using conventional scanning electron microscopes (CD SEM). Higher CD spatial
resolutions can be achieved using advanced inspection tools, which provide CD data on a substantially smaller length
scale (10-4 m), thus yielding a considerably larger CD snapshot for front/backup process tool comparisons. Combining
PCA analysis with high spatial resolution CD data provides novel insights into the opportunities for tool and process CD
Pending the availability of actinic inspection tools, optical inspection tools with 193 nm DUV
illumination wavelength are currently used to inspect EUV masks and EUVL-exposed wafers.
Due to strong optical absorption, DUV photons can penetrate only a few surface layers of EUV
masks, making them sub-optimal for detecting hidden defects embedded within the sub-layers of
the mask, the so-called phase defects. Although these phase defects may not be detected by
optical inspection tools, they may print on the wafer. Conversely, false and nuisance defects
which may not print on the wafer may be detected by optical inspection tools, and by so doing,
degrade the inspection sensitivity of the tool to real and critical defects. This paper discusses
approaches to optimizing the optical inspection sensitivity of EUV masks, with a view to
overcoming some of the absorption limitations of the inspection wavelength and also with a view
to enhancing the imaging contrast of the reflected light between the low reflective absorber/antireflection
coating stack and the moderately reflective mirror surface of Mo/Si bilayers, capped
with a thin Ru layer, and which serves to protect the mirror surface from damage and
contamination during mask fabrication and wafer printing processes. The effects of mask
absorber/ARC stack thickness on optical inspection contrast are simulated using rigorous
coupled wave analysis (RCWA), and compared to experimental results. EUV masks with thin
absorber/ARC stacks are observed to have higher inspection contrast, up to 15 % higher than
their thicker counterparts, especially as the feature pitch gets smaller. Blank defect inspection
performance of tools such as the Siemens DFX40 tool and KLA 617 Teron tool equipped with
Phasur module are compared, and correlated with patterned mask inspection data generated from
KLA 617 Teron tool. Patterned mask defect sensitivities to the tune of 40 nm and 90 nm were
obtained on thin and thick absorber/ARC stacks, respectively. The defect location accuracy of
the Teron 617 tool is better than 250 nm (3σ), while the alignment repeatability of the Teron 617
on the fiducials is better than 60 nm (3σ). Printability of mask blank and patterned mask defects
on exposed wafers in terms of what and where the defects print, are also presented. Four masks
with different absorber and antireflection coating thicknesses, some with substrate and absorber programmed defects of different types and sizes, were fabricated and used to expose resistcoated
SiN substrate wafers on full field ASML EUV scanners.
Critical dimensions (CD) measured in resist are key to understanding the CD distribution on photomasks. Vital to this
understanding is the separation of spatially random and systematic contributions to the CD distribution. Random
contributions will not appear in post etch CD measurements (final) whereas systematic contributions will strongly impact
final CDs. Resist CD signatures and their variations drive final CD distributions, thus an understanding of the mechanisms
influencing the resist CD signature and its variation play a pivotal role in CD distribution improvements. Current
technological demands require strict control of reticle critical dimension uniformity (CDU) and the Advanced Mask
Technology Center (AMTC) has found significant reductions in reticle CDU are enabled through the statistical analysis of
large data sets. To this end, we employ Principle Component Analysis (PCA) - a methodology well established at the
AMTC1- to show how different portions of the lithographic process contribute to CD variations. These portions include
photomask blank preparation as well as a correction parameter in the front end process. CD variations were markedly
changed by modulating these two lithographic portions, leading to improved final CDU on test reticles in two different
chemically amplified resist (CAR) processes.
The continued shrink of integrated circuit patterns increases the demand for reticle enhancement techniques (RET). The
application of Sub Resolution Assist Features (SRAFs) is pushing mask processes to the resolution limit. Many
Chemically Amplified Resists (CAR) used in current photomask processes do not have the capability to fully meet the
current demand for SRAF resolution.
Often the resulting quality of small SRAFs suffers from pattern fidelity limitations like Line End Shorting (LES) and
corner rounding. While small SRAFs might physically resolve on the mask, these limitations cause massive nuisance
detections at defect inspections. In a productive environment, high levels of nuisance detections are not acceptable due to
the cycle time impact from classification and review.
The AMTC systematically investigated the SRAF capability of different mask processes in order to better understand the
process limitations as well as to predict the manufacturability of customer patterns. This investigation uses high
sensitivity inspections of a specially designed test pattern to determine the SRAF capability limits. An overview of the
predicted SRAF capabilities for different resists and blank substrates is provided along with verification on customer
Reticle critical dimension (CD) errors must be minimized in order for photomask manufacturers to meet tight CD uniformity
(CDU) requirements. Determining the source of reticle CD errors and reducing or eliminating their CDU contributions are
some of the most relevant tasks facing process engineers. The AMTC has applied principal component analysis (PCA) to
reticle resist CD measurements in order to examine variations in the data. PCA provided the major components of resist CD
variation which were rescaled into reticle CD signatures. The dominant component of CD signature variation is very similar
in shape and magnitude between two different chemically amplified resist (CAR) processes, most likely indicating the
variation source is a common process or tool. CD variational signatures from PCA were used as a basis for launching
investigations into potential reticle CD error sources. PCA was further applied to resist CD measurements from alternate
process tools to assist efforts in judging the effectiveness of resist CD signature matching.
Laser lithography tools have been a staple in the photomask industry for second level printing for several years. This paper explores the overlay capabilities of the Alta4300D Deep UV (DUV) lithography system. The tool is manufactured by ETEC Systems, a part of the Mask Business Group of Applied Materials. The tool demonstrates good overlay performance, and an improved data path ensures the ability to handle large file sizes without an adverse impact on writing time. In addition to actual performance data on product masks, a simple analysis of the maximum total edge placement error of a hypothetical two level alt-PSM process is presented. The results show the tool is capable for many advanced phase shift overlay applications.
Recently, the design of integrated circuits has become more and more complicated due to higher circuit densities. In particular for logic applications, the design is no longer uniform but combines different kinds of circuits into one mask layout resulting in stringent criteria for both wafer and photomask manufacturing. Photomask CD uniformity control and defectivity are two key criteria in manufacturing today’s high-end reticles, and they are both strongly impacted by the mask developing process.
A new photomask develop tool (ACT-M) designed by Tokyo Electron Limited (TEL) has been installed at the Advanced Mask Technology Center (AMTC) in Dresden, Germany. This ACT-M develop tool is equipped with a standard NLD nozzle as well as an SH nozzle which are both widely used in wafer developing applications. The AMTC and TEL used the ACT-M develop tool to adapt wafer puddle develop technology to photomask manufacturing, in an attempt to capture the same optimum CD control enjoyed by the wafer industry. In this study we used the ACT-M develop tool to examine CD uniformity, local loading and defect control on P-CAR and N-CAR photomasks exposed with 50keV e-beam pattern generators. Results with both nozzle types are reported. CD uniformity, loading, and defectivity results were sufficient to meet 65-nm technology node requirements with these nozzles and tailored made develop recipes for photomask processing.
The challenges, mask manufacturing is faced with, are more and more dominating the semiconductor industry as the pattern sizes shrink. Today's mask patterns have reached sizes that are common in wafer manufacturing. Looking into the industry, we can see that some of the quality parameters - such as CD uniformity and defect control - are managed better in wafer than in mask manufacturing. Consequently, mask manufacturers have started to apply more wafer processing techniques to mask processes. Among others, develop process has a great impact on the quality of the mask manufacturing. This contribution describes how Tokyo Electron Limited (TEL) scanning (linear drive nozzle) developer processing (widely used in advanced wafer manufacturing) was adapted for mask development. Out of this technology transfer, a new alpha-type mask develop tool was launched at TEL and an evaluation of this tool was carried out at the Advanced Mask Technology Center (AMTC), Dresden, Germany. Target of this collaboration was to successfully transfer wafer processing technology to mask making. By this, valuable information was generated, that has been implemented into the production platform, which is commercialized since first half of 2004.
A new photomask develop tool designed by Tokyo Electron Limited (TEL) with wafer puddle technology was evaluated at the Advanced Mask Technology Center (AMTC) in Dresden, Germany. Parameters selected for this evaluation were resist dark loss uniformity, critical dimension (CD) uniformity, loading, linearity, resist cross sectional images, and defects using chemically amplified resists (CARs) exposed with DUV (l=257nm) and 50KeV e-beam pattern generators. Implementing wafer puddle technology to photomask developing was not a simple, straightforward process. Standard CAR puddle recipes for wafer developing were inadequate to match CDU requirements for photomasks at the 130nm technology node using DUV exposure. While the results were disappointing, the TEL alpha develop tool cannot be held entirely responsible. Other, non-develop tool related factors such as resist, substrate, coating bake temperature and time, lithography tool, and post exposure bake temperature and time, all contributed to the final post develop results. Indeed, other CAR/substrate combinations exposed at 50keV e-beam and processed on the TEL alpha develop tool were markedly better in CD performance when compared to DUV results. The AMTC has recently taken delivery of a full scale, production worthy, TEL photomask develop tool for use at future technology nodes.
Laser pattern generators have demonstrated cost-effective reticle manufacturing for critical layers down to the 180nm generation. This paper considers the issues that will need to be resolved to allow laser pattern generators to pattern critical levels for 130nm and 90nm node technology. The performance of current Wafer Optical lithography systems is used as a benchmark. The differences between Wafer and Reticle lithography, in particular, image formation, resist processing, substrate design and etch requirements are all discussed. Areas where wafer lithography expertise can benefit mask makers are discussed and approaches to extend Laser pattern generators down to 200nm feature sizes and below are suggested.