Up until now, the main driving force for the semiconductor industry is the continual shrinkage of device feature sizes, thereby incorporating more devices per unit area, reducing manufacturing cost and enhancing their performance have been achieved. However, the shrinkage of feature size leads to a reduction of process window imposing an extremely tight requirement for parameters such as critical dimension (CD), edge and width roughness of spaces/trenches, contacts, lines, and tip to tip (T2T) values. At sub 14 nm technology nodes these parameters have a significant influence on the overall device performance. With EUV based pattering becoming the sole option at these advanced nodes, a thorough characterization of the patterning process is of utmost importance before it can be a high-volume manufacturing solution.<p> </p> In this work, we show how e-beam inspection has been used to characterize a single exposure EUV M2 (Metal 2 layer, BEoL) to have an understanding of the different hotspots and intra-field signatures present. Design Based Metrology (DBM) with wide SEM image was employed to measure CD distribution and Edge Placement Error (EPE) distribution of metal layer pattern on the 10nm logic wafer.