Proceedings Article | 25 May 2017
Proc. SPIE. 10146, Advances in Patterning Materials and Processes XXXIV
KEYWORDS: Wafer-level optics, Lithography, Polishing, Optical lithography, Etching, Glasses, Ultraviolet radiation, Semiconducting wafers, Surface finishing, Chemical mechanical planarization
Planarization is a critical unit step in the lithography process because it enables patterning of surfaces with versatile pattern density without compromising on the stringent planarity and depth-of-focus requirements. In addition to nanoscale pattern density variation, parasitics such as pre-existing wafer topography, can corrupt the desired process output after planarization. The topography of any surface can be classified in three broad categories, depending upon the amplitude and spatial wavelength of the same [1], [2]: (i) nominal shape, (ii) nanotopography and (iii) roughness. The nominal shape is given by the largest spatial wavelengths, typically < 20mm. For spatial length scales of ~1-20mm, height variations at this spatial wavelength range are classified as nanotopography. Roughness usually has lower spatial wavelengths. While the nominal shape of a substrate surface is usually decided by the nature of wafer preparation and the tooling and chucking infrastructure used in the same, roughness is usually mitigated by standard polishing techniques. It is the intermediate nanotopography that is probably the most critical surface topography parameter. This is because most traditional polishing techniques cannot selectively address pre-existing substrate topography, without introducing a parasitic signature at the scale of nanotopography. Moreover, fields with pattern density variation typically also have length scales that are commensurate with nanotopography. It is thus instructive to summarize existing planarization technology to understand current limitations.
Spin on Glass and Etch back is one technique used for micron scale device manufacturing [3]. As the name implies, a glass dielectric is spin-coated on the substrate followed by etching in a chemistry that ensures equal etching rates for both the sacrificial glass and the underlying film or substrate material. Photoresists may also be used instead of glass. However, the global planarity that can be achieved by this technique is limited. Also, planarization over a large isolated topographical feature has been studied for the reverse-tone Jet-and-Flash Imprint Lithography process, also known as JFIL-R [4]. This relies on surface tension and capillary effects to smoothen a spin-coated Si containing film that can be etched to obtain a smooth profile.
To meet the stringent requirement of planarity in submicron device technologies Chemical Mechanical Planarization (CMP) is the most widely used planarization technology [5], [6]. It uses a combination of abrasive laden chemical slurry and a mechanical pad for achieving planar profiles. The biggest concern with CMP is the dependence of material removal rate on the pattern density of material, leading to the formation of a step between the high density and low-density. The step shows up as a long-range thickness variation in the planarized film, similar in scale to pre-existing substrate topography that should have been polished away. Preventive techniques like dummy fill and patterned resist can be used to reduce the variation in pattern density. These techniques increase the complexity of the planarization process and significantly limit the device design flexibility.
Contact Planarization (CP) has also been reported as an alternative to the CMP processing [7], [8]. A substrate is spin coated with a photo curable material and pre baked to remove residual solvent. An ultra-flat surface or an optical flat is pressed on the spin-coated wafer. The material is forced to reflow. Pressure is used to spread out material evenly and achieve global planarization. The substrate is then exposed to UV radiation to harden the photo curable material. Although attractive, this process is not adaptive as it does not account for differences in surface topography of the wafer and the optical flat, nor can it address all the parasitics that arise during the process itself. The optical flat leads to undesirable planarization of even the substrate nominal shape and nanotopography, which corrupts the final film thickness profile. Hence, it becomes extremely difficult to eliminate this signature to a desirable extent without introducing other parasitic signatures. An example of this is shown in Figure 1.
In this paper, a novel adaptive planarization process has been presented that potentially addresses the problems associated with planarization of varying pattern density, even in the presence of pre-existing substrate topography [9]. This process is called Inkjet-enabled Adaptive Planarization (IAP). The IAP process uses an inverse optimization scheme, built around a validated fluid mechanics-based forward model [10], that takes the pre-existing substrate topography and pattern layout as inputs. It then generates an inkjet drop pattern with a material distribution that is correlated with the desired planarization film profile. This allows a contiguous film to be formed with the desired thickness variation to cater to the topography and any parasitic signatures caused by the pattern layout. This film is formed by the coercing action of a compliant superstrate, which forces the drops to spread and merge and eliminates any bubble trapping. Then, the film is cured using blanket UV exposure and the superstrate separated to reveal the desired planarized film. The use of an inverse optimization algorithm allows substrate topography to be addressed adaptively. In other words, the algorithm can generate a drop pattern that does not disturb the pre-existing substrate topography substantially, but only caters to the pattern density variation. This process has potential advantages over other planarization techniques because of its adaptive nature. Hence, the IAP process can cater to substrates of varying topographies and pattern densities by changing the inkjetted material distribution, without any changes in hardware. The IAP process can also address pre-existing substrate topography selectively by conforming to the nominal shape while planarizing over the pattern layout. A schematic of the IAP process is shown in Figure 2.
The goal of this paper is to present some preliminary results from the IAP process. A test pattern layout has been generated with the help of photolithography, and is shown in Figure 3. For the purpose of this trial, the nanoscale features have not been patterned, as it is expected that the planarization process will be blind to their presence. Thus, areas with nanoscale patterns have been patterned as a single feature of SiO2 with height equal to 100 nm. These features are adjacent to pattern-less areas, thus marking a drastic change in pattern density. As can be seen in Figure 4, the smallest length scale across which pattern density changes, is 70 microns. The goal of the IAP process is to be able to planarize this pattern with a film that conforms to pre-existing substrate topography. The targeted planarity of the film is 95% 3sigma, while the targeted film thickness at the tallest feature is less than 30 nm. In another trial, the inverse tone of the same layout will also be tested. This pattern has features of height equal to 100 nm where the previous pattern did not. The targeted metrics for the inverse layout are the same as the nominal layout.
