Detecting and resolving the true on-wafer-hotspot (defect) is critical to improve wafers’ yield in high volume manufacturing semiconductor foundries. Traditionally, Optical Rule Check (ORC) with computation lithography has been one of the most important techniques to flag potential failure patterns (weak points) after Optical Proximity Correction (OPC), where ORC results are fed back to the OPC team to fix the OPC solution if needed, or fed forward to Contamination Free Manufacturing (CFM) team to improve the inspection accuracy. However, as the integrated circuits process becomes more and more complex with the technology scaling, ORC alone could no longer identify the outlier-alike defects, even though it has helped in resolving most of defects on wafer. Failing to detect yield-killer defects could be due to the lack of sufficient understanding and modeling in terms of etching, CMP, as well as other inter-layer process variations. It has been a struggle for Fab to identify reasonable amount of defects scattered on wafer in order to understand defect mechanisms quickly, thus find ways to fix them in a timely manner. In this paper, we present a fast and accurate Defect Detection and Repair Flow (DDRF) with machine learning (ML) methodology to address the above issues. There are four parts in the DDRF: the first part is on the feature generation and data collection, the second on the ML model building, the third on the full-chip prediction, and the fourth on the hot-spot repair. We use limited amount of known defects found on wafer as input to train the ML model, and then apply the ML model to the full chip for prediction. The wafer verification data showed that our flow achieved more than 80% of defect hit rate with engineered feature extractions and ML model for a 7nm mask. Finally, we analyze the failing mechanism with more available defects, and are able to provide guidance to the OPC development to fix the defects by using the ML model.
Finding the true on-product hot spots (patterning defects) by High Volume Manufacturing (HVM) inspection tools is increasingly challenging as the process window margin shrinks. It is a common practice nowadays to use Optical Rule Check (ORC) results by computation lithography to provide “care areas” to increase the signal to noise level of the inspection tool, thus improving the detection accuracy. The care area defined by the traditional method of contour-based process window checks may not be good enough. There are cases where real yield killers were not caught by contour-based checks, resulting in missing errors during wafer inspection as well. In this paper, we expand the traditional process window checks to a broader lithographic spectrum. The method allows us to utilize additional limiters such as max intensity, contrast, and NILS checks in combination with normal CD-based checks such as bridge, pinch, or process window bands to achieve higher accuracy in failure locations. This compound check will be trained using existing on product failure data obtained from low and high resolution wafer inspection as well as eTest and yield data. The combination of contour and intensity-based checks is demonstrated to be more effective in capturing the wafer hot spots for new products. The various usage models of such enhanced ORC will also be discussed.
CDSEM metrology is a powerful tool to obtain silicon data. However, as our technology nodes advance shrink to 14nm and below, the CD measurement data from CDSEM can hardly provide sufficient information for OPC verification (OPCV) and the related silicon verification. On the other hand, the abundant information from CDSEM images has not been fully utilized to assist our data analysis. In this context, contour extraction emerges as the best method to obtain extensive information from CDSEM images, especially for 2D structures. This paper demonstrates that contour extraction bridges the gap between the needs of 2D characterization and the limited capability of CDSEM measurement. The extracted contour enables automatic identification of litho-hotspots using OPCV tools, especially for non-CD related hotspots. Statistical silicon data extraction and analysis on complex geometries is viable with extracted contours. The silicon data can then be feedback to the evolution of non-CD OPCV checks, where simple CD measurement is inadequate. Effective CD can also be calculated from the obtained 2D information, with which Bossung curves can be built and provide complementary information.
The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer.
This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.
The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to develop, or “queue time”, is studied in detail. The impact of time link delay on resolved critical dimension (CD) is fully characterized for patterned resist and etched geometries as a function of various process changes. In this study, we assembled a detailed, theoretical model and performed experimental work to correlated time link delay to acid diffusion within the resist polymer matrix. Acid diffusion is determined using both a modulation transfer function for diffusion and simple approximation based on Fick’s law of diffusion.
With shrinking feature sizes and error budgets in OPC models, effective pattern coverage and accurate measurement
become more and more challenging. The goal of pattern selection is to maximize the efficiency of gauges used in model
calibration. By optimizing sample plan for model calibration, we can reduce the metrology requirement and modeling
turn-around time, without sacrificing the model accuracy and stability. With the Tachyon pattern-selection-tool, we seek
to parameterize the patterns, by assessing dominant characteristics of the surroundings of the point of interest. This
allows us to represent each pattern with one vector in a finite-dimensional space, and the entire patterns pool with a set
of vectors. A reduced but representative set of patterns can then be automatically selected from the original full set
sample data, based on certain coverage criteria. In this paper, we prove that the model built with 56% reduced wafer data
could achieve comparable quality as the model built with full set data.