Continued improvement in pattern fidelity and reduction in total edge placement errors are critical to enable yield and scaling in advanced devices. In this work, we discuss patterning optimization in a combined two-layer process, using ArFi self-aligned double patterned line and EUV via process in a 10nm test vehicle. In prior work (1), we showed the composite correction ability for lithography and etch systems in single layer processes. Here, we expand on the optimization and setup to improve the single layer process, improve the line edge roughness, and look at a second layer via process. The sum of all those optimizations is the edge placement. Here, we describe the fidelity of the final multilayer pattern and the process budget for a two-layer line and via process in terms of total edge placement error (EPE) (2). In the line process, control of mechanical interactions in the resist and etch process significantly improve line width and line edge roughness (LWR/LER), with a net improvement in LWR of 30% measured after develop, and 18% measured after etch. Pitchwalk is improved using cross wafer etch and litho cooptimization to less than 1.0nm 3σ. For the via process, we determine the root distribution of EPE resulting from the core placement errors at lithography and etch. Results on final multilayer pattern uniformity, overlay, and edge placement are shown.