When the size of a CMOS imaging sensor array is fixed, the only way to increase sampling density and spatial resolution is to reduce pixel size. But reducing pixel size reduces the light sensitivity. Hence, under these constraints, there is a tradeoff between spatial resolution and light sensitivity. Because this tradeoff involves the interaction of many different system components, we used a full system simulation to characterize performance. This paper describes system simulations that predict the output of imaging sensors with the same dye size but different pixel sizes and presents metrics that quantify the spatial resolution and light sensitivity for these different imaging sensors.
Earlier studies have shown that multiple capture can achieve high SNR, but cannot satisfy the high dynamic range (HDR) and high speed
requirements of the Vertically-Integrated-Sensor-Array (VISA)
project. Synchronous self-reset, on the other hand, can achieve these
requirements, but suffers from poor SNR. Extended counting can
achieve high dynamic range at high frame rate and with good SNR, but
at the expense of high power consumption. The paper proposes a new
HDR focal plane array architecture, denoted by folded-multiple capture (FMC), which by combining features of the synchronous self-reset and multiple capture schemes, can satisfy the VISA requirements at a fraction of the power dissipation and with more robustness to device variations than extended counting. The architecture is also capable of detecting subframe disturbances, e.g., due to laser jamming, and correcting for it.
The paper investigates the suitability of ΣΔ modulation
based FPA readout schemes for use in Vertically Interconnected Sensor
Arrays requiring ultra high dynamic range and frame rate. It is shown
that the extended counting scheme is capable of achieving the DR and
frame rate requirements but at the expense of high power consumption. Extended counting is also shown to outperform several other HDR schemes in terms of SNR at the ultra high DR and frame rate.
Proc. SPIE. 5301, Sensors and Camera Systems for Scientific, Industrial, and Digital Photography Applications V
KEYWORDS: Signal to noise ratio, Digital signal processing, High dynamic range image sensors, Sensors, Modulators, Image sensors, Quantization, High dynamic range imaging, Cadmium sulfide, Signal detection
Analysis of dynamic-range (DR) and signal-to-noise-ratio (SNR) for high fidelity, high-dynamic-range (HDR) image sensor architectures is presented. Four architectures are considered: (i) time-to-saturation, (ii) multiple-capture, (iii) asynchronous self-reset with multiple capture, and (iv) synchronous self-reset with residue readout. The analysis takes into account circuit nonidealities such as quantization noise and the effects of limited pixel area on building block and reference signal performance and accuracy. Examples that demonstrate the behavior of SNR in the extended DR and implementation and power consumption issues for each scheme are presented.
A method for synthesizing enhanced depth of field digital still camera
pictures using multiple differently focused images is presented. This
technique exploits only spatial image gradients in the initial
decision process. The image gradient as a focus measure has been
shown to be experimentally valid and theoretically sound under weak
assumptions with respect to unimodality and monotonicity. Subsequent majority filtering corroborates decisions with those of neighboring pixels, while the use of soft decisions enables smooth transitions across region
boundaries. Furthermore, these last two steps add algorithmic
robustness for coping with both sensor noise and optics-related
effects, such as misregistration or optical flow, and minor intensity
fluctuations. The dependence of these optical effects on several
optical parameters is analyzed and potential remedies that can allay
their impact with regard to the technique's limitations are
discussed. Several examples of image synthesis using the algorithm are
presented. Finally, leveraging the increasing functionality and
emerging processing capabilities of digital still cameras, the method
is shown to entail modest hardware requirements and is implementable
using a parallel or general purpose processor.