Dr. Sam Nakagawa Profile

Dr. Sam Nakagawa

at GlobalFoundries

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Publications (2)

Proceedings Article | 26 May 2022 Presentation + Paper

Wafer level analysis and simulation of back end of line chemical mechanical polishing processes

Ushasree Katakamsetty, Stefan Nikolaev Voykov, Sascha Bott, Sam Nakagawa, Tamba Tugbawa, Aaron Gower-Hall, Brian Lee, Jansen Chee, Henry Geng, Weiyang Zhu, Bifeng Li, Kimiko Ichikawa

Proceedings Volume 12052, 1205212 (2022) https://doi.org/10.1117/12.2616078

KEYWORDS: Chemical mechanical planarization, Semiconducting wafers, Data modeling, Calibration, Dysprosium, Back end of line, Polishing, Design for manufacturing, Metals, Chemical reactions

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Proceedings Article | 22 February 2021 Presentation + Paper

Guard-banding of IP against topography sensitivity using silicon-calibrated CMP model

Ushasree Katakamsetty, Sam Nakagawa, Ernesto Gene de la Garza, Ruben Ghulghazaryan, Davit Piliposyan, Simon Favre, Jeff Wilson

Proceedings Volume 11614, 116140Y (2021) https://doi.org/10.1117/12.2585488

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In semiconductor manufacturing, intellectual property (IP) cores/blocks play a dominant role in modern chip design. The driving factor for IP usage is the time-to-market benefit delivered through design reuse. Today, IP blocks include the entire range of modules, ranging from standard cells, memories, and I/O devices to CPUs. Chip designers need complex IP blocks because modern levels of integration allow chips to be a complete system on chip (SOC), not just components of systems. However, as chips become more complex, IP blocks are subject to more interactions from multiple neighboring modules in the chip. Current IP block quality assurance (QA) flows focus mainly on functional verification, performance verification, and design rule checking (DRC). The standard DRC deck checks for minimum and maximum density rules within the IP block. However, when an IP is placed in an SOC, it may encounter complex surrounding scenarios, as when a low density IP is placed next to a higher density area. During integrated circuit (IC) manufacturing, the resulting proximity effects may cause failures or electrical targeting mismatches within the IP, due to etch micro-loading and long-range CMP interactions. Designers can only locate these chemical mechanical polishing (CMP) hotspots related to IP placement in the SOC near the end of the design flow, which limits any floorplan changes to fix the hotspots. Standalone IP block QA is insufficient to detect possible layout- or floorplan-induced problems that can affect manufacturing. In this paper, we present a CMP modeling methodology to guard-band IP against topography variations that can occur after IP placement in the SOC design. We emulate low, average, and high-density scenarios surrounding the IP blocks, followed by CMP simulations and hotspot detection using silicon-calibrated CMP models. After simulation, guidelines provided to fix these CMP hotspots surrounding the IP blocks during early design stages to improve manufacturability and yield. This flow will make IPs robust from CMP hotspots that typically appear after SOC floorplanning.

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