Multi-beam mask writer MBM-1000 is developed for N5. It is designed to accomplish higher throughput than a singlebeam
VSB writer EBM-9500 at shot count higher than 500 G/pass, and write masks with low sensitivity resist to have
better CDU and patterning resolution. Product version of blanking aperture array (BAA) for MBM-1000 is fabricated
along with data transfer system to accomplish data rate of 300 Gbps. They have been integrated with writing control
software based on MBF format, a tool-specific format which handles any-angle pattern and polygon patterns. Writing
test without re-adjustment of beam current showed that exposure time control by BAA blanking is very stable, and linear
CD drift is less than 0.1 nm for 10 hours. Complex OPC pattern and ring pattern were printed on low-sensitivity pCAR
resist and showed good resolution to resolve 25 nm isolated line.
Multi-beam mask writer is under development to solve the throughput and patterning resolution problems in
VSB mask writer. Theoretically, the writing time is appropriate for future design node and the resolution is
improved with multi-beam mask writer. Many previous studies show the feasible results of resolution, CD
control and registration. Although such technical results of development tool seem to be enough for mass
production, there are still many unexpected problems for real mass production.
In this report, the technical challenges of multi-beam mask writer are discussed in terms of production and
application. The problems and issues are defined based on the performance of current development tool
compared with the requirements of mask quality. Using the simulation and experiment, we analyze the specific
characteristics of electron beam in multi-beam mask writer scheme. Consequently, we suggest necessary
specifications for mass production with multi-beam mask writer in the future.
Recently, Multi-Beam Mask Writer (MBMW) scheme is newly considered for next generation writing scheme. As the
MBMW writing uses many multi-array bundle beams with small spot size, the fast writing and complex pattering is
The target dose level of MBMW is high around 100μC/cm2 and the target of total writing time is within 10 hours for
next generation layout with complex and small node pattern. The risks of high dose writing are rising of blank
temperature, chemical reaction with photo-resist and charging effects in blank. In addition, the fast writing can cause the
rising of temperature in blank.
The heating effect can be divided into local and global terms, and each effect of critical dimension (CD) and
registration was analyzed by heating effect. In case of MBMW, the global heating is more critical than local heating.
Therefore, we need to study about the global heating effect which can affect global registration in MBMW.
In this paper, we study about the global heat distribution on mask blank in certain MBMW writing condition, and the
directional deformation of blank which can affect global registration was analyzed by using Finite Element Method
(FEM). We approach with two kinds of modified heat model and the FEM model was verified with analytical calculation.
The temperature variation and deformation distribution were achieved with transient method with the writing
conditions, in case of 100μC/cm2 of total dose, 50kV of acceleration voltage, 100% of chip density and 10 hour of total writing time. Therefore, we can consider the writing conditions according to mask specification in MBMW scheme.
Because mask patterning quality of CD uniformity, MTT, registration and smaller assist feature size is important for wafer patterning, the higher exposure dose and complex pattern design will be necessary. It is the reason why the faster and more accurate e-beam mask writer is needed for future design node. Multi-beam mask writer is the most promising new e-beam mask writer technology for future sub-10nm device mask patterning to solve the pattern quality issue and writing time problem. In this report, the technical challenges of multi-beam mask writer are discussed by comparison with problems of current VSB e-beam mask writer. Comparing with e-beam mask writer which has the critical issues of beam size and position control, the application of entirely different methods and techniques of CD and position control is essential for multi-beam mask writer which has new architecture and writing strategy. Using the simulation method, we present the different challenges between VSB and multi-beam mask writer. And there are many important technical requirements to achieve expected specification of multi-beam mask writer. To understand such requirements, the patterning simulation and mathematical calculation are done for analysis. Based on the patterning simulation, the detail technical requirements and issues of multi-beam mask writer are achieved. Consequently, we suggest the direction of multi-beam mask writer development in terms of technical challenges and requirements.
As semiconductor features shrink in size and pitch, the extreme control of CD uniformity, MTT and image placement
is needed for mask fabrication with e-beam lithography. Among the many sources of CD and image placement error,
the error resulting from e-beam mask writer becomes more important than before. CD and positioning error by e-beam
mask writer is mainly related to the imperfection of e-beam deflection accuracy in optic system and the charging and
contamination of column. To avoid these errors, the e-beam mask writer should be designed taking into account for
these effects. However, the writing speed is considered for machine design with the highest priority, because the e-beam
shot count is increased rapidly due to design shrink and aggressive OPC. The increment of shot count can make the
pattern shift problem due to statistical issue resulting from e-beam deflection error and the total shot count in layout.
And it affects the quality of CD and image placement too.
In this report, the statistical approach on CD and image placement error caused by e-beam shot position error is
presented. It is estimated for various writing conditions including the intrinsic e-beam positioning error of VSB writer.
From the simulation study, the required e-beam shot position accuracy to avoid pattern shift problem in 22nm node and
beyond is estimated taking into account for total shot count. And the required local CD uniformity is calculated for
various e-beam writing conditions. The image placement error is also simulated for various conditions including e-beam
writing field position error. Consequently, the requirements for the future e-beam mask writer and the writing
conditions are discussed. And in terms of e-beam shot noise, LER caused by exposure dose and shot position error is
studied for future e-beam mask writing for 22nm node and beyond.
The ray tracing of electron based on Monte Carlo is simulated by GEANT software to investigate the electron scattering
property in ArF photomask and EUV photomask. By Monte Carlo simulation, we have presented the mechanism of
electron scattering in EUV photomask and simulated the electron distribution which gives rise to change the patterning
performance of EUV photomask, compared with those of ArF photomask. Furthermore, the overlay error of EUV
photomask has been analyzed by the charging model.
EUV photomask has the additional electron distribution in the range of 2um, which comes from the strong electron
scattering at Mo/Si multilayer. Because of this additional electron distribution, EUV photomask has the pattern size
error due to proximity effect of electron when the conventional Gaussian function is used to correct the proximity effect
of ArF photomask. The maximum residual error due to the proximity effect in EUV photomask is 7nm. Furthermore, we
have confirmed that the linearity of pattern size is so different from ArF photomask and it is well explained with the
Gaussian blur model based on the electron distribution of EUV photomask.
As semiconductor features shrink in size and pitch, there are strong needs for an advanced mask writer which has better
patterning quality. Among various requirements for next photomask writer, we have focused on the requirements of ebeam
size and position accuracy for hp 32nm and beyond generation.
At the era of DPT, EUV, and complex OPC, the photomask is required to have extreme control of critical dimension
(CD). Based on simulation and experiment, we present the e-beam requirements for advanced mask writer, in view
point of stability and accuracy. In detail, the control of e-beam size in mask writer should be decreased to 0.5nm
because the size error of e-beam gives rise to large CD error according to the high complexity of mask pattern.
Furthermore, the drift error of beam position should be smaller than 1nm to obtain the tight pattern placement error and
to minimize the edge roughness of mask pattern for the era of computational lithography and EUV lithography.
As semiconductor features shrink in size and pitch, the extreme control of CD uniformity and MTT is needed for
mask fabrication with e-beam lithography. And because of huge shot density of data, the writing time of e-beam
lithography for mask fabrication will be increased rapidly in future design node.
The beam drift caused by charging of optic system and current density drift can affect the beam size, position and
exposure dose stability. From the empirical data, those are the function of writing time. Although e-beam lithography
tool has the correction function which can be applied during writing, there are remained errors after correction which
result in CD uniformity error. According to the writing time increasing, the residual error of correction will be more
important and give the limit of CD uniformity and MTT.
In this study, we study the beam size and exposure dose error as a function of time. Those are mainly caused by
charging and current density drift. And we present the predicted writing time of e-beam lithography below 32nm node
and estimate its effect on CD control error. From the relation between writing time and CD control error, we achieve the
limit of CD uniformity with e-beam mask writer. And we suggest the method to achieve required CD uniformity at
22nm node and beyond.
Recent Low k1 era requires aggressive OPC technology with advanced lithography technology. The aggressive OPC
contains the rounded pattern and a lot of assistant pattern which are the main source to increase the shot division. We
have defined the shot complexity, which is defined by the ratio of number of shot between the interested pattern and the
1:1 L/S pattern. Based on shot complexity parameter, we have estimated the writing time as the device node decreases.
We expect that the aggressive OPC and the high dose could generate severely the writing time issue in 32nm node era.
As semiconductor features shrink in size and pitch, the image placement error at photomask has been interested as an
important factor to be reduced. Especially, by the development of double exposure technique (DET) or double
patterning technique (DPT) for sub-45 nm node the image placement error is required to be controlled tightly.
Following ITRS roadmap, when DET or DPT is used the registration for sub-45 nm node is required to be less than 4
nm but this specification still corresponds to the challengeable goal. Among various sources of image placement errors,
here, we focus on the error occurring at patterning process of photomask and discuss its effect on the photomask
overlay. We name the image placement error occurred at patterning process due to e-beam charging effect, absorber
etching effect, and so on as the pattern loading effect. We quantify the amount of pattern loading effect on registration
error, analyze it with the help of simulation and experiment, and discuss the character of each error and correction
As semiconductor features shrink in size and pitch, the pattern placement error at photomask, that is, the registration
becomes more important factor to be reduced. Following ITRS roadmap, the registration for sub-45 nm node is required
to be less than 5 nm but this specification still corresponds to the challengeable goal. Among several reasons to induce
registration, here, we have focused on four major registration errors: e-beam positioning error, patterning effect, pellicle
attachment effect, and sampling error of measurement. We quantify and analyze each error with the help of finite
element modeling and by experiment. Based on these results, we present the current status and the goal of each error for
the roadmap of sub-45 nm node.
The tight MTT control is required for the mask process of sub-50nm design node due to the complex OPC and
insufficient process margin. The MTT below 5nm is already required for the critical layers. Below 4nm is required for
sub-50nm node. In the viewpoint of this requirement, the MTT control is important for the mask fabrication.
According to the shrinking design node, the linearity is the main issue to satisfy MTT required. In the electron beam (ebeam)
lithography, the linearity results are strongly related to the resolution of the mask process. Isolated and dense
patterns have the different linearity behaviors due to the different contrast mainly caused by the backward scattering
contribution and develop process. Because of this reason, the conventional method of proximity effect correction (PEC)
optimization is unlikely to satisfy the MTT requirement. New PEC optimization is necessary for sub-50nm node.
In this report, new PEC optimization method is proposed. This method reduces the PEC error of conventional
optimization method known as a few nm. Because of the linearity, the error of conventional PEC optimization is
amplified according to the shrinking design. Therefore, the PEC error of conventional method is larger than the MTT
requirement for sub-50nm node. This new method is designed to overcome this problem. It takes into account for the
properties of each layer. Based on the analysis of composition of each layer, the different PEC optimization to fit the
each layer and design node is applied. It is able to be applied for the mask fabrication of sub-50nm memory device. The
improvement of MTT is achieved by the reduction of the PEC error with new PEC optimization.
With decreasing the design node, there are some candidates for the optical lithography technology. Double Exposure
Technology (DET) is the one of the solution to extend the resolution limit down to k1 less than 0.25 for the next
generation devices. To accomplish DET, photomask MTT, CD uniformity, and the overlay between the layers for the
dual exposure are important as the photomask process aspect.
MTT and CD uniformity have been frequently discussed for Single Exposure Technology (SET), but the overlay and
the registration have not been discussed yet with the view of DET. In this work, the feasibility of mask fabrication,
especially the overlay and the registration for DET are analyzed. The current mask limit of DET is discussed
considering MTT, uniformity, and overlay.
For the half pitch below 45nm, the required sub-resolution feature size is about to be 60nm, and the uniformity of dense
lines to be below 3.4nm for the mask fabrication. To achieve this requirement, the reduction of beam blur is necessary.
On the mask patterning using 50keV electron beam, the beam blurring due to coulomb interaction and resist
characteristics is the main effect of the pattern image degradation and the limit of CD uniformity.
In this report, we present the effect of the beam blur induced by coulomb interaction and resist. And we report the recent
simulated and experimental results on the resolution change depending on bream blur and design node. Finally, we
conclude that the reduction of beam blur can improve the mask quality and there is a compatible condition between the
beam blur and the mask fabrication.
In order to make the mask for the photolithography, e-beam direct writing system has been used because e-beam source is most controllable among the direct systems. However, the development of the new e-beam system is scheduled slowly and there is no conspicuous breakthrough technology to improve the quality of the mask comparing to the wafer exposure tool development. Lately, a new laser writing system, Sigma7300 is introduced and shows 200x reduction projection system and very high throughput relative to the e-beam direct writing system. Because it can write the full layout in a mask less than 4
hours, the high reproducibility is expected. Although the current tool is using KrF light source and 0.82NA reduction projection lens column, the higher resolution tool using the ArF light source can be expected in the future. In this paper the possible resolution limit of the Sigma7300 is discussed and the application example for the mask fabrication. To estimate the process capability, the optical simulation is performed and compared with the experimental results. Because its patterned image is not so clear like the e-beam writer, the pattern rounding, the line-end shortening, and the minimum assist feature are discussed with the patterns of the e-beam writer. At the end the important qualities of the mask like defects are compared with the results of the e-beam system.
Proc. SPIE. 6283, Photomask and Next-Generation Lithography Mask Technology XIII
KEYWORDS: Electron beam lithography, Electron beams, Data modeling, Backscatter, Scattering, Laser scattering, Monte Carlo methods, Photomasks, Critical dimension metrology, Vestigial sideband modulation
Recently, the mask writing technology with 50keV electron beam energy is close to its resolution limit. It will be hard to achieve 30nm node mask pattern in near future. Especially the writing of OPC and 2-D patterns will be critical issue. Furthermore, according to the shrinking of pattern, the tight mask CD uniformity is required due to large MEEF. About 2.4nm mask CD uniformity will be required in terms of 3σ.
In this report, we analyze the beam energy effect on the resolution improvement using the quantitative analysis of beam blurring including the resist effect. From the experimental result, the total blur is about 45.57nm with 50keV VSB and 43.70nm with 100keV spot beam. And we compare the dose margin and linearity for each case. Dose margin by 50keV VSB is 0.96nm/%dose and 0.89nm/%dose for 100keV spot beam. We conclude that the effect by the increasing of electron beam energy is not so much significant and the reduction of the blur by electron beam column is as much as efficient. And finally we calculate the limitation of CD uniformity for each case.
Implementation of high resolution E-beam tools is an attractive candidate for next generation lithography. To understand the forward scattering blur and proximity in 100kV E-beam tool, we studied E-beam acceleration voltage effects on dose sensitivity and iso-dense CD bias. We measured and analyzed the dose sensitivity (nm/%dose) near the design CD using various local density patterns. Proximity effects due to backscattering were much larger in 100keV exposure and caused the degraded dose sensitivity. We made a simple model and analyzed each contribution from a resist process, forward scattering and backscattering. We concluded that backscattering was the major reason of decreasing ILS(Image Log Slope) and the difference of forward scattering blur between 50 and 100 keV was negligible. Backscattering contribution compared to that of forward scattering was two times larger in the 100keV exposure, which can make accurate CD control difficult.
The correction of fogging effect from an electron beam writer and loading effect from a dry etcher are known as the important factors of non-uniformity of mask CD. To achieve the improvement of CD uniformity, the fogging and loading effect are modeled as a function of pattern density. Taking into account the different behavior of fogging and loading effect on the pattern density, the amount of correction is able to be extracted using the promising modeling and dose modulation technique. In this work, we report the evaluation of correction method with improved model using the linear combination of fogging and loading effect. We compared the various cases and presented the best result of the improvement of CD uniformity.