It is necessary to make small sized flash cells for high density flash products and it is indispensable to minimize the line and space widths of Metal lines in such a high density Flash chips. To minimize a line and space widths, the thickness of photo resists must be reduced for the process margin of photo lithography. but the reduced thickness of photo resists is normally not enough for metal etch. So hard masks are needed for metal etch. In this study we have made a metal-etch process with KrF photo resists and oxide hard mask which has lines and spaces with 120 by 120nm. We have used TEOS film as an oxide hard mask for metal etch and have made an ex-situ process to open the hard mask for metal etch, in this ex-situ hard-mask-open process we have had bad line-edge-roughness (LER) problems but we have found out the main effective parameters for LER by DOE methods and various experiments and have finally optimized the process conditions. After the hard-mask-open process, metal line can be patterned with photo resist and oxide hard mask. The side wall profile of metal lines made by oxide hard mask are different from those made by normal photo resist mask because the types and quantities of by-products from oxide masks are different from those from photo resists during etch process. Normally by-products or polymer could be re-deposited to the side wall of metal lines, so they could be protected from possible side-wall-attacks. However due to the lack of by-products from oxides, the side wall of metal lines could be damaged if they were etched only with oxide-hard-masks, so we have had a experiment of metal lines' profile characteristics according to the ratio of photo resist's thickness to oxide hard mask's thickness, and have found out that the ratio of photo resist to oxide hard mask has a significant role in metal line profiles. Despite those side wall profile problems, eventually we have optimized a condition by adjusting the proper thickness of oxide-hard-masks and by tuning the process gas in the series of etch process. Finally in 90nm s-Flash device fabrication, we have made the metal lines with the same high qualities as those of 130nm devices from the view point of profiles and Electro Migration characteristics.
In this study, we reported on the evaluation result of the optimized high voltage gate patterning in liquid crystal
display (LCD) driver integrated circuit (IC) with its preparation, characterization and composition of each parameter
such as etching gas chemistry, RF power, and pressure. The patterning process of high voltage gate oxide was
performed with the CF<sub>4</sub>/CHF<sub>3</sub>/O<sub>2</sub>/Ar based gas chemistry to avoid the leakage current from high voltage gate stack by
non-uniform remnant gate oxide thickness. Albeit we obtained the minimized fluctuation of gate oxide thickness, the
plasma damage by plasma patterning process affected the leakage current of high voltage gate film stack.
In conclusion, we found that the major parameter for leakage current in high voltage gate stack by DOE method of gate
patterning and achieved that the optimized condition of high voltage gate patterning. To optimize the performance of
high voltage gate oxide, the thickness of remnant oxide must be controlled uniformly in gate patterning for improving
the margin of high voltage gate transistor. Verifying that the patterning performance of physical and electrical
characteristics with analytical tools such as secondary ion mass spectroscopy (SIMS), scanning electron microscopy
(SEM), auger electron spectroscopy (AES) and probe station as well.
We investigated that Shallow Trench Isolation (STI) dry etching process using SiO2 hard-mask and KrF photo-resist in
90nm stand-alone flash device. As shrinkage of design rule, the thickness of photo-resist is reduced because of guarantee
for process margin in photolithographic process, but the etch process margin is smaller. For the reason, the hard-mask system for etch is needed. Generally, the STI dry etching process is composed of two or three steps, such as the ARC etch, the hard-mask etch, and the Si etch. In order to etch multi-stacked layer (ARC, Oxide hard-mask (SiO2), Si<sub>3</sub>N<sub>4</sub> as CMP stopping layer, and Si), we have controlled the parameters of etching (plasma power, gas, and pressure). In the SiO<sub>2</sub> hard-mask and Si<sub>3</sub>N<sub>4</sub> layer etching process, we use a mixture chemistry of CF<sub>4</sub>, CHF<sub>3</sub>, O<sub>2</sub>, and Ar and get an optimized condition for the multi-layer system. The SiO<sub>2</sub> layer is role of mask for Si layer because the selectivity between SiO<sub>2</sub> and Si is superior to others. Finally, we get a good horizontal and vertical profile of STI by using a mixture chemistry of Cl<sub>2</sub>, HBr, and O<sub>2</sub>.