As the design rule shrinks down, various techniques such as RET, DFM have been continuously developed and
applied to lithography field. And we have struggled not only to obtain sufficient process window with those
techniques but also to feedback hot spots to OPC process for yield improvement in mass production. OPC
verification procedure which iterates its processes from OPC to wafer verification until the CD targets are met and
hot spots are cleared is becoming more important to ensure robust and accurate patterning and tight hot spot
Generally, wafer verification results which demonstrate how well OPC corrections are made need to be fed back to
OPC engineer in effective and accurate way. First of all, however, it is not possible to cover all transistors in full-chip
with some OPC monitoring points which have been used for wafer verification. Secondly, the hot spots which
are extracted by OPC simulator are not always reliable enough to represent defective information for full-chip.
Finally, it takes much TAT and labor to do this with CD SEM measurement. These difficulties on wafer verification
would be improved by design based analysis. The optimal OPC monitoring points are created by classifying all
transistors in full chip layout and Hotspot set is selected by pattern matching process using the NanoScope<sup>TM</sup>, which
is known as a fast design based analysis tool, with a very small amount of hotspots extracted by OPC simulator in
full chip layout. Then, each set is used for wafer verification using design based inspection tool, NGR2150<sup>TM</sup>. In this
paper, new verification methodology based on design based analysis will be introduced as an alternative method for
effective control of OPC accuracy and hot spot management.