To accord with new requirement of securing more overlay margin, not only the optical overlay measurement is faced with the technical limitations to represent cell pattern’s behavior, but also the larger measurement samples are inevitable for minimizing statistical errors and better estimation of circumstance in a lot. From these reasons, diffraction based overlay (DBO) and integrated metrology (IM) were mainly proposed as new approaches for overlay enhancement in this paper.
In recent semiconductor manufacturing, hardmask is unavoidable requirement to further transfer the patterning from
thin photoresist to underlayer. While several types of hardmask materials have been investigated, amorphous carbon has
been attractive for good etching resistance and high-aspect-ratio resolution. However, it has fatal problem with lowering
overlay controllability due to its high extinction coefficient (k). Thus, the correlation of alignment and overlay
performance with varying hardmask materials is required to meet a tight overlay budget of 2x nm node and beyond. In
this paper, we have investigated the effects of the hardmask materials with respect to the optical properties on the
performance of overlay applicable to 2x nm memory devices.
The extension of optical lithography to 2Xnm and beyond is often challenged by overlay control. With reduced overlay
measurement error budget in the sub-nm range, conventional Total Measurement Uncertainty (TMU) data is no longer
sufficient. Also there is no sufficient criterion in overlay accuracy. In recent years, numerous authors have reported new
method of the accuracy of the overlay metrology: Through focus and through color. Still quantifying uncertainty in
overlay measurement is most difficult work in overlay metrology. According to the ITRS roadmap, total overlay budget
is getting tighter than former device node as a design rule shrink on each device node. Conventionally, the total overlay
budget is defined as the square root of square sum of the following contributions: the scanner overlay performance,
wafer process, metrology and mask registration. All components have been supplying sufficiently performance tool to
each device nodes, delivering new scanner, new metrology tools, and new mask e-beam writers. Especially the scanner
overlay performance was drastically decreased from 9nm in 8x node to 2.5nm in 3x node. The scanner overlay seems to
reach the limitation the overlay performance after 3x nod. The importance of the wafer process overlay as a contribution
of total wafer overlay became more important. In fact, the wafer process overlay was decreased by 3nm between DRAM
8x node and DRAM 3x node. We develop an analytical algorithm for overlay accuracy. And a concept of nondestructive
method is proposed in this paper. For on product layer we discovered the layer has overlay inaccuracy. Also
we use find out source of the overlay error though the new technique.
In this paper, authors suggest an analytical algorithm for overlay accuracy. And a concept of non-destructive method is
proposed in this paper. For on product layers, we discovered it has overlay inaccuracy. Also we use find out source of
the overlay error though the new technique. Furthermore total overlay error data is decomposed into two parts: the
systematic error and the random error. And we tried to show both error components characteristic, systematic error has a
good correlation with residual error by scanner condition, whereas, random error has a good correlation with residual
error as going process steps. Furthermore, we demonstrate the practical using case with proposed method that shows the
working of the high order method through systematic error. Our results show that to characterize an overlay data that is
suitable for use in advanced technology nodes requires much more than just evaluating the conventional metrology
metrics of TIS and TMU.