An 8-inch wafer scale process was developed that provides low cost availability of back-side illuminated (BSI) imaging sensors. The process has been optimized to convert standard CMOS and CCD 6-inch or 8-inch wafers from front side illuminated (FSI) sensors to BSI sensors. The process successfully demonstrates wafer planarization, bow correction, bonding to carrier wafers, wafer thinning, re-planarization, anti-reflection coating, through silicon vias (TSVs) and back side metallization. Good wafer thinning control was obtained for a wide range of epi thicknesses varying from 4 microns to 15 microns. The thinner epi is optimized for UV and visible sensing while the thicker epi material is optimized for near-infrared (NIR) sensing. The processed wafers demonstrate backside passivation and anti-reflection (AR) coatings that optimize the QE performance in a variety of bands such as 200nm-300nm, 300nm-400nm and 400nm-900nm.
Three-dimensional read-out integrated circuit (3D-ROIC) based advanced focal-plane-array (FPA) architectures are driven by the requirements of pixel level analog-to-digital conversion, on-chip digital-signal-processing, high framerates, low read noise, and extended dynamic range. These 3D-ROIC FPAs require hybridization of analog technology ROIC silicon wafers with digital technology ROIC silicon wafers and detectors. Small pitch vias are needed both at the topmost and bottommost surfaces of the analog wafers to facilitate these 3D-ROIC architectures. Although it is easy to build top surface vias, integration of bottom surface vias into the CMOS process flows is uncommon. In this paper, we describe the integration of tungsten-filled isolated deep-silicon-vias (iDSV) extending from metal1 to the handle wafer of the substrate in thick-film SOI based 130nm and 180nm mixed-signal CMOS processes. Major advantages of the iDSV based integration scheme reported here include ease of porting of mixed-signal designs from bulk CMOS to SOI, high density 3D-ROIC interconnect formation with via-middle integration, and an inbuilt buried-oxide etch stop layer for post wafer process thinning for iDSV reveal. These iDSVs have resistances of 2.5Ω/via, breakdown voltages exceeding 50V, and leakage currents to adjacent wells of less than 10fA/via. We report electrical results and process flow of the more complex face-to-back hybrid wafer bonding utilizing the top vias in the daughter wafer and iDSV in the mother wafer with copper direct-bond-interconnect (DBI) hybridization at 4μm pitch. We outline various 3D-ROIC integration architectures for large-format and small pixel FPAs using iDSV and DBI bonding, along with their advantages and disadvantages.